ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 227

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.13.10 INTCTRLB – Interrupt Control register B
18.13.11 INTFLAGSACLR/ INTFLAGSASET – Clear/ Set Interrupt Flag register A
8291A–AVR–10/11
• Bit 5 – BUSERRIE: Bus Error Interrupt Enable
Setting this bit will enable the interrupt for the following three bus error events:
The INTLVL bits must be nonzero for the interrupts to be generated.
• Bit 4 – STALLIE: STALL Interrupt Enable
Setting this bit enables the STALL interrupt for the conditions that set the stall interrupt flag
(STALLIF) in the INTFLAGSACLR/SET register. The INTLVL bits must be nonzero for the inter-
rupts to be generated.
• Bit 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1:0 – INTLVL[1:0]: Interrupt Level
These bits enable the USB interrupts and select the interrupt level, as described in
and Programmable Multilevel Interrupt Controller” on page
source must be separately enabled.
• Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1 – TRNIE: Transaction Complete Interrupt Enable
Setting this bit enables the transaction complete interrupt for IN and OUT transactions. The
INTLVL bits must be nonzero for interrupts to be generated.
• Bit 0 – SETUPIE: SETUP Transaction Complete Interrupt Enable
Setting this bit enables the SETUP Transaction Complete Interrupt for SETUP transactions. The
INTLVL bits must be non-zero for the interrupts to be generated.
This register is mapped into two I/O memory locations, one for clearing (INTFLAGSACLR) and
one for setting (INTFLAGSASET) the flags. The individual flags can be set by writing a one to
their bit locations in INFLAGSASET, and cleared by writing a one to their bit locations in INT--
Bit
+0x07
Read/Write
Initial Value
1. Isochronous CRC Error: An interrupt will be generated for the conditions that set the
2. Underflow: An interrupt will be generated for the conditions that set the undeflow inter-
3. Overflow: An interrupt will be generated for the conditions that set the overflow interrupt
CRC interrupt flag (CRCIF) in the INTFLAGSACLR/SET register during isochronous
transfers.
rupt flag (UNFIF) in the INTFLAGSACLR/SET register.
flag (OVFIF) in the INTFLAGSACLR/SET register.
R
7
–
0
R
6
–
0
R
5
–
0
R
4
–
0
R
3
–
0
Atmel AVR XMEGA B
133. In addition, each USB interrupt
R
2
–
0
TRNIE
R/W
1
0
SETUPIE
R/W
0
0
”Interrupts
INTCTRLB
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