ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 217

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.6
8291A–AVR–10/11
Ping-pong Operation
Figure 18-7. Clock generation configuration.
When an endpoint is configured for ping-pong operation, it uses the input and output data buf-
fers to create a single, double-buffered endpoint that can be set to input or output direction. This
provides double-buffered communication, as the CPU or DMA controller can access one of the
buffers, while the other buffer is processing an ongoing transfer. Ping-pong operation is identical
to the IN and OUT transactions described above, unless otherwise noted in this section. Ping-
pong operation is not possible for control endpoints.
When ping-pong operation is enabled for an endpoint, the endpoint in the opposite direction
must be disabled. The data buffer, data pointer, byte counter, and auxiliary data from the
enabled endpoint are used as bank 0, and, correspondingly, bank 1 for the opposite endpoint
direction.
The bank select (BANK) flag in the endpoint STATUS register indicates which data bank will be
u s e d i n t h e n e x t t r a n s a c t i o n . I t i s u p d a t e d a f t e r e a c h t r a n s a c t i o n . T h e
TRNCOMPL0/TRNCOMPL1, underflow/overflow (UDF/OVF), and CRC flags in the STATUS
register are set for either the enabled or the opposite endpoint direction according to the BANK
flag. The data toggle (TOGGLE), data buffer 0/1 not acknowledge (BUSNACK0 and
BUSNACK1), and BANK flags are updated for the enabled endpoint direction only.
USB module
48MHz full speed
6MHz for low speed
USB clock
prescaler
USBPSDIV
Atmel AVR XMEGA B
USBSRC
48MHz Internal Oscillator
PLL
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