ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 401

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Notes:
29.12.3.1
29.12.3.2
8291A–AVR–10/11
CMD[6:0]
Boot Loader Section
Calibration and User Signature Sections
Fuses and Lock Bits
EEPROM Page Buffer
EEPROM
0x2A
0x2C
0x2D
0x1A
0x4C
0x38
0x68
0x39
0x01
0x18
0x02
0x07
0x08
0x33
0x36
0x30
0x32
0x34
0x35
0x06
1. If the EESAVE fuse is programmed, the EEPROM is preserved during chip erase.
Chip Erase
Read NVM
Commands / Operation
Application section CRC
Erase boot section
Erase boot loader section page
Write boot loader section page
Erase and write boot loader section page
Boot loader section CRC
Read user signature row
Erase user signature row
Write user signature row
Read calibration row
Read fuse
Write fuse
Write lock bits
Load EEPROM page buffer
Erase EEPROM page buffer
Erase EEPROM
Erase EEPROM page
Write EEPROM page
Erase and write EEPROM page
Read EEPROM
The chip erase command is used to erase the flash program memory, EEPROM and lock bits.
Erasing of the EEPROM depends on EESAVE fuse setting. Refer to
5” on page 33
Once this operation starts, the PDI bus between the PDI controller and the NVM is disabled, and
the NVMEN bit in the PDI STATUS register is cleared until the operation is finished. Poll the
NVMEN bit until this is set, indicating that the PDI bus is enabled.
The BUSY flag in the NVM STATUS register will be set until the operation is finished.
The read NVM command is used to read the flash, EEPROM, fuses, and signature and calibra-
tion row sections.
1. Load the NVM CMD register with the chip erase command.
2. Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence
during self-programming.
for details. The user signature row, calibration row, and fuses are not affected.
Atmel AVR XMEGA B
Trigger
CMDEX
PDI write
PDI write
PDI write
PDI write
NVMAA
PDI read
PDI write
PDI write
PDI read
PDI read
PDI write
CMDEX
PDI write
CMDEX
CMDEX
PDI write
PDI write
PDI write
PDI read
”FUSEBYTE5 – Fuse Byte
Change
Protected
Y
N
N
N
N
Y
N
N
N
N
N
N
Y
N
Y
Y
N
N
N
N
NVM Busy
Y
Y
Y
Y
Y
Y
N
Y
Y
N
N
Y
Y
N
Y
Y
Y
Y
Y
N
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