ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 218

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ATxmega128B1

Manufacturer Part Number
ATxmega128B1
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega128B1

Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
53
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
10
Input Capture Channels
10
Pwm Channels
10
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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18.7
18.7.1
8291A–AVR–10/11
Multipacket Transfers
For Input Endpoints
Figure 18-8. Ping-pong operation overview.
Multipacket transfer enables a data payload exceeding the maximum data payload size of an
endpoint to be transferred as multiple packets without any software intervention. This reduces
interrupts and software intervention to the higher level USB transfer, and frees up significant
CPU time. Multipacket transfer is identical to the IN and OUT transactions described above,
unless otherwise noted in this section.
The application software provides the size and address of the SRAM buffer to be processed by
the USB module for a specific endpoint, and the USB module will then split the buffer in the
required USB data transfer.
Figure 18-9. Multipacket overview.
The total number of data bytes to be sent is written to CNT, as for normal operation. The auxil-
iary data register (AUXDATA) is used to store the number of bytes that will be sent, and must be
written to zero for a new transfer.
With multipacket
Without multipacket
With Ping-Pong
Without Ping-Pong
Transfer Complete Interrupt and data processing
USB data packet
Available time for data processing by CPU to avoid NACK
Atmel AVR XMEGA B
t
t
Double bank
single bank
Endpoint
Endpoint
Bank0
Bank1
218

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