ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 283
ATxmega128B1
Manufacturer Part Number
ATxmega128B1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128B1
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
53
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
10
Input Capture Channels
10
Pwm Channels
10
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128B1-AU
Manufacturer:
TI
Quantity:
90
Company:
Part Number:
ATxmega128B1-U
Manufacturer:
FUJITSU
Quantity:
632
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21.15 Register Description
21.15.1
21.15.2
8291A–AVR–10/11
DATA – Data register
STATUS – Status register
The USART transmit data buffer register (TXB) and USART receive data buffer register (RXB)
share the same I/O address and is referred to as USART data register (DATA). The TXB register
is the destination for data written to the DATA register location. Reading the DATA register loca-
tion returns the contents of the RXB register.
For 5-bit, 6-bit, or 7-bit characters, the upper unused bits will be ignored by the transmitter and
set to zero by the receiver.
The transmit buffer can be written only when DREIF in the STATUS register is set. Data written
to the DATA register when DREIF is not set will be ignored by the USART transmitter. When
data are written to the transmit buffer and the transmitter is enabled, the transmitter will load the
data into the transmit shift register when the shift register is empty. The data are then transmit-
ted on the TxD pin.
The receive buffer consists of a two-level FIFO. Always read STATUS before DATA in order to
get the correct status of the receive buffer.
• Bit 7 – RXCIF: Receive Complete Interrupt Flag
This flag is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). When the receiver is disabled, the
receive buffer will be flushed, and consequently RXCIF will become zero.
When interrupt-driven data reception is used, the receive complete interrupt routine must read
the received data from DATA in order to clear RXCIF. If not, a new interrupt will occur directly
after the return from the current interrupt. This flag can also be cleared by writing a one to its bit
location.
• Bit 6 – TXCIF: Transmit Complete Interrupt Flag
This flag is set when the entire frame in the transmit shift register has been shifted out and there
are no new data in the transmit buffer (DATA). TXCIF is automatically cleared when the transmit
complete interrupt vector is executed. The flag can also be cleared by writing a one to its bit
location.
Bit
+0x00
Read/Write
Initial Value
Bit
+0x01
Read/Write
Initial Value
RXCIF
R
7
0
R/W
7
0
TXCIF
R/W
6
0
R/W
6
0
DREIF
R
5
1
R/W
5
0
FERR
R
4
0
R/W
4
0
RXB[[7:0]
BUFOVF
TXB[[7:0]
R
3
0
Atmel AVR XMEGA B
R/W
3
0
PERR
R
2
0
R/W
2
0
1
–
R
0
R/W
1
0
RXB8
R/W
0
0
STATUS
R/W
0
0
283
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