ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 384

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.3
29.4
29.4.1
29.4.2
29.4.3
29.4.4
29.5
8291A–AVR–10/11
NVM Controller
NVM Commands
NVM Controller Busy Status
Action-triggered Commands
NVM Read-triggered Commands
NVM Write-triggered Commands
Write/Execute Protection
The device can be locked to prevent reading and/or writing of the NVM. There are separate lock
bits for external programming access and self-programming access to the boot loader section,
application section, and application table section.
Access to the nonvolatile memories is done through the NVM controller. It controls NVM timing
and access privileges, and holds the status of the NVM, and is the common NVM interface for
both external programming and self-programming. For more details, refer to
tion” on page
The NVM controller has a set of commands used to perform tasks on the NVM. This is done by
writing the selected command to the NVM command register. In addition, data and addresses
must be read/written from/to the NVM data and address registers for memory read/write
operations.
When a selected command is loaded and address and data are set up for the operation, each
command has a trigger that will start the operation. Based on these triggers, there are three
main types of commands.
Action-triggered commands are triggered when the command execute (CMDEX) bit in the NVM
control register A (CTRLA) is written. Action-triggered commands typically are used for opera-
tions which do not read or write the NVM, such as the CRC check.
NVM read-triggered commands are triggered when the NVM is read, and this is typically used
for NVM read operations.
NVM write-triggered commands are triggered when the NVM is written, and this is typically used
for NVM write operations.
Most command triggers are protected from accidental modification/execution during self-pro-
gramming. This is done using the configuration change protection (CCP) feature, which requires
a special write or execute sequence in order to change a bit or execute an instruction. For
details on the CCP, refer to
When the NVM controller is busy performing an operation, the busy flag in the NVM status regis-
ter is set and the following registers are blocked for write access:
• NVM command register
• NVM control A register
• NVM control B register
• NVM address registers
• NVM data registers
404.
”Configuration Change Protection” on page
Atmel AVR XMEGA B
12.
”Register Descrip-
384