ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 252

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.9.4
8291A–AVR–10/11
STATUS – Status register
STOP condition. The ACKACT bit and the CMD bits can be written at the same time, and then
the acknowledge action will be updated before the command is triggered.
Table 19-5.
Writing a command to the CMD bits will clear the master interrupt flags and the CLKHOLD flag.
• Bit 7
This flag is set when a byte is successfully received in master read mode; i.e., no arbitration was
lost or bus error occurred during the operation. Writing a one to this bit location will clear RIF.
When this flag is set, the master forces the SCL line low, stretching the TWI clock period. Clear-
ing the interrupt flags will release the SCL line.
This flag is also cleared automatically when:
• Bit 6
This flagis set when a byte is transmitted in master write mode. The flag is set regardless of the
occurrence of a bus error or an arbitration lost condition. WIF is also set if arbitration is lost dur-
ing sending of a NACK in master read mode, and if issuing a START condition when the bus
state is unknown. Writing a one to this bit location will clear WIF. When this flag is set, the mas-
ter forces the SCL line low, stretching the TWI clock period. Clearing the interrupt flags will
release the SCL line.
The flag is also cleared automatically for the same conditions as RIF.
Bit
+0x03
Read/Write
Initial Value
• Writing to the ADDR register
• Writing to the DATA register
• Reading the DATA register
• Writing a valid command to the CMD bits in the CTRLC register
CMD[1:0]
–
–
00
01
10
11
RIF: Read Interrupt Flag
WIF: Write Interrupt Flag
R/W
RIF
7
0
CMD bits description.
WIF
R/W
Configuration
6
0
BYTEREC
NOACT
START
Group
STOP
CLKHOLD
R
5
0
RXACK
R
4
0
MODE
W
X
X
R
X
ARBLOST
R/W
3
0
Atmel AVR XMEGA B
Operation
Reserved
Execute acknowledge action succeeded by
repeated START condition
No operation
Execute acknowledge action succeeded by
a byte receive
Execute acknowledge action succeeded by
issuing a STOP condition
BUSERR
R/W
2
0
R/W
1
0
BUSSTATE[1:0]
R/W
0
0
STATUS
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