ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 179

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ATxmega128B1

Manufacturer Part Number
ATxmega128B1
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega128B1

Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
53
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
10
Input Capture Channels
10
Pwm Channels
10
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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14.6
14.6.1
14.6.2
8291A–AVR–10/11
Compare Channel
Waveform Generation
Single-slope PWM Generation
Figure 14-4. Changing the period.
Each compare channel continuously compares the counter value with the CMPx register. If CNT
equals CMPx, the comparator signals a match. For the low-byte timer/counter, the match will set
the compare channel's interrupt flag at the next timer clock cycle, and the event and optional
interrupt is generated. The high-byte timer/counter does not have compare interrupt/event.
The compare channels can be used for waveform generation on the corresponding port pins. To
make the waveform visible on the connected port pin, the following requirements must be
fulfilled:
Inverted waveform output can be achieved by setting invert I/O on the port pin. Refer to
Ports” on page 142
For PWM generation, the period (T) is controlled by the PER register, while the CMPx registers
control the duty cycle of the waveform generator (WG) output.
how the counter counts from TOP to BOTTOM, and then restarts from TOP. The WG output is
set on the compare match between the CNT and CMPx registers, and cleared at BOTTOM.
Figure 14-5. Single-slope pulse width modulation.
CNT
1. The compare channels to be used must be enabled. This will override the correspond-
2. The direction for the associated port pin must be set to output.
CNT
WG Output
ing port pin output register.
BOTTOM
BOTTOM
MAX
MAX
TOP
CMPx
New TOP written to
PER that is higher
than current CNT
for more details.
Period (T)
CMPx=TOP
New TOP written to
PER that is lower
than current CNT
Atmel AVR XMEGA B
Figure 14-5 on page 179
CMPx=BOT
"reload"
"write"
"match"
shows
”I/O
179

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