ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 54

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.13
5.13.1
8291A–AVR–10/11
Register Description – DMA Controller
CTRL – Control Register
• Bit 7 – ENABLE: Enable
Setting this bit enables the DMA controller. If the DMA controller is enabled and this bit is written
to zero, the ENABLE bit is not cleared before the internal transfer buffer is empty, and the DMA
data transfer is aborted.
• Bit 6 – RESET: Software Reset
Writing a one to RESET will be ignored as long as DMA is enabled (ENABLE = 1). This bit can
be set only when the DMA controller is disabled (ENABLE = 0).
• Bit 5:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 2 – DBUFMODE: Double Buffer Mode
This bit enables the double buffer on the channels according to
Table 5-1.
• Bit 1 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bit 0 – PRIMODE: Channel Priority Mode
This bit determines the internal channel priority according to
Table 5-2.
Bit
+0x00
Read/Write
Initial Value
DBUFMODE
PRIMODE
0
1
0
1
ENABLE
R/W
7
0
DMA double buffer settings.
DMA channel priority settings.
RR01
CH01
Group Configuration
DISABLED
CH01
Group Configuration
RESET
R/W
6
0
R
5
–
0
R
4
–
0
No double buffer enabled
Description
Round robin
Channel0 > Channel1
Description
Double buffer enabled on channel0/1
R
3
–
0
Atmel AVR XMEGA B
DBUFMODE
Table
R/W
2
0
Table
5-2.
5-1.
R
1
–
0
PRIMODE
R/W
0
0
CTRL
54