ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 155
ATxmega128B1
Manufacturer Part Number
ATxmega128B1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128B1
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
53
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
10
Input Capture Channels
10
Pwm Channels
10
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128B1-AU
Manufacturer:
TI
Quantity:
90
Company:
Part Number:
ATxmega128B1-U
Manufacturer:
FUJITSU
Quantity:
632
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13.6
13.6.1
8291A–AVR–10/11
Counter Operation
Normal Operation
Figure 13-4. Period and compare double buffering.
When the CC channels are used for a capture operation, a similar double buffering mechanism
is used, but in this case the buffer valid flag is set on the capture event, as shown in
For capture, the buffer register and the corresponding CCx register act like a FIFO. When the
CC register is empty or read, any content in the buffer register is passed to the CC register. The
buffer valid flag is passed to set the CCx interrupt flag (IF) and generate the optional interrupt.
Figure 13-5. Capture double buffering.
Both the CCx and CCxBUF registers are available as an I/O register. This allows initialization
and bypassing of the buffer register and the double buffering function.
Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decre-
mented at each timer/counter clock input.
In normal operation, the counter will count in the direction set by the direction (DIR) bit for each
clock until it reaches TOP or BOTTOM. When up-counting and TOP is reached, the counter will
be set to zero when the next clock is given. When down-counting, the counter is reloaded with
the period register value when BOTTOM is reached.
UPDATE
"capture"
"INT/DMA
request"
BV
IF
BV
EN
EN
"write enable"
CCxBUF
data read
EN
EN
CCx
CNT
CNT
Atmel AVR XMEGA B
"data write"
CCxBUF
=
CCx
"match"
Figure
13-5.
155
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