ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 232

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.14.3
8291A–AVR–10/11
CNTL – Counter Low
interrupts or software intervention. See
packet transfers.
• Bit 4 – PINGPONG: Ping-pong Enable
Setting this bit enables ping-pong operation. Ping-pong operation enables both endpoints (IN
and OUT) with same address to be used in the same direction to allow double buffering and
maximize throughput. The endpoint in the opposite direction must be disabled when ping-pong
operation is enabled. Ping-pong operation is not possible for control endpoints. See
Operation” on page 217
• Bit 3 – INTDSBL: Interrupt Disable
Setting this bit disables all enabled interrupts from the endpoint. Hence, only the interrupt flags
in the STATUS register are updated when interrupt conditions occur. The FIFO does not store
this endpoint configuration table address upon transaction complete for the endpoint when inter-
rupts are disabled for an endpoint. Clearing this bit enables all previously enables interrupts
again.
• Bit 2 – STALL: Endpoint STALL
This bit controls the STALL behavior if the endpoint.
• Bit 1:0 – BUFSIZE[1:0]: Data Size
These bits configure the maximum data payload size for the endpoint. Incoming data bytes
exceeding the maximum data payload size are discarded.
• Bit 2:0 – BUFSIZE[2:0]: Data Size
These bits configure the maximum data payload size for the endpoint when configured for iso-
chronous operation.
Table 18-5.
Note:
The CNTL and CNTH registers represent the 10-bit value, CNT, that contains the number of
bytes received in the last OUT or SETUP transaction for an OUT endpoint, or the number of
bytes to be sent in the next IN transaction for an IN endpoint.
BUFSIZE[2:0]
100
101
110
111
000
001
010
011
1. Setting only available for isochronous endpoints.
(1)
(1)
(1)
(1)
BUFSIZE configuration.
Group Configuration
for details.
1023
128
256
512
16
32
64
8
”Multipacket Transfers” on page 218
Description
8-byte buffer size
16-byte buffer size
32-byte buffer size
64-byte buffer size
128-byte buffer size
256-byte buffer size
512-byte buffer size
1023-bytesbuffer size
Atmel AVR XMEGA B
for details on multi-
”Ping-pong
232