ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 255

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.10 Register Description – TWI Slave
19.10.1
8291A–AVR–10/11
CTRLA
–
Control register A
register can only be accessed when the SCL line is held low by the master; i.e., when CLKHOLD
is set.
In master write mode, writing the DATA register will trigger a data byte transfer followed by the
master receiving the acknowledge bit from the slave. WIF and CLKHOLD are set.
In master read mode, RIF and CLKHOLD are set when one byte is received in the DATA regis-
ter. If smart mode is enabled, reading the DATA register will trigger the bus operation as set by
the ACKACT bit. If a bus error occurs during reception, WIF and BUSERR are set instead of
RIF.
Accessing the DATA register will clear the master interrupt flags and CLKHOLD.
• Bit 7:6
These bits select the interrupt level for the TWI master interrupt, as described in
Programmable Multilevel Interrupt Controller” on page
• Bit 5
Setting the data interrupt enable (DIEN) bit enables the data interrupt when the data interrupt
flag (DIF) in the STATUS register is set. The INTLVL bits must be nonzero for the interrupt to be
generated.
• Bit 4
Setting the address/stop interrupt enable (APIEN) bit enables the address/stop interrupt when
the address/stop interrupt flag (APIF) in the STATUS register is set. The INTLVL bits must be
nonzero for interrupt to be generated.
• Bit 3
Setting this bit enables the TWI slave.
• Bit 2
Setting the this bit will cause APIF in the STATUS register to be set when a STOP condition is
detected.
• Bit 1
By setting the this bit, the slave address match logic responds to all received addresses. If this
bit is cleared, the address match logic uses the ADDR register to determine which address to
recognize as its own address.
Bit
+0x00
Read/Write
Initial Value
–
–
–
–
–
–
DIEN: Data Interrupt Enable
APIEN: Address/Stop Interrupt Enable
ENABLE: Enable TWI Slave
PIEN: Stop Interrupt Enable
PMEN: Promiscuous Mode Enable
INTLVL[1:0]: Interrupt Level
R/W
7
0
INTLVL[1:0]
R/W
6
0
DIEN
R/W
5
0
APIEN
R/W
4
0
ENABLE
R/W
3
0
133.
Atmel AVR XMEGA B
PIEN
R/W
2
0
PMEN
R/W
1
0
SMEN
R/W
”Interrupts and
0
0
CTRLA
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