ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 259

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.10.5
19.10.6
8291A–AVR–10/11
DATA
ADDRMASK
–
Data register
–
When using 10-bit addressing, the address match logic only supports hardware address recog-
nition of the first byte of a 10-bit address. By setting ADDR[7:1] = 0b11110nn, ”nn” represents
bits 9 and 8 of the slave address. The next byte received is bits 7 to 0 in the 10-bit address, and
this must be handled by software.
When the address match logic detects that a valid address byte is received, APIF is set and the
DIR flag is updated.
If the PMEN bit in CTRLA is set, the address match logic responds to all addresses transmitted
on the TWI bus. The ADDR register is not used in this mode.
The data (DATA) register is used when transmitting and received data. During data transfer,
data are shifted from/to the DATA register and to/from the bus. This implies that the DATA regis-
ter cannot be accessed during byte transfers, and this is prevented by hardware. The DATA
register can be accessed only when the SCL line is held low by the slave; i.e., when CLKHOLD
is set.
When a master is reading data from the slave, data to send must be written to the DATA regis-
ter. The byte transfer is started when the master starts to clock the data byte from the slave,
followed by the slave receiving the acknowledge bit from the master. DIF and CLKHOLD are set.
When a master writes data to the slave, DIF and CLKHOLD are set when one byte has been
received in the DATA register. If smart mode is enabled, reading the DATA register will trigger
the bus operation as set by the ACKACT bit.
Accessing the DATA register will clear the slave interrupt flags and CLKHOLD. When an
address match occurs, the received address will be stored in the DATA register.
Address Mask register
• Bit 7:1
These bits can act as a second address match register or as an address mask register, depend-
ing on the ADDREN setting.
If ADDREN is set to zero, ADDRMASK can be loaded with a 7-bit slave address mask. Each bit
in ADDRMASK can mask (disable) the corresponding address bit in the ADDR register. If the
mask bit is one, the address match between the incoming address bit and the corresponding bit
in ADDR is ignored; i.e., masked bits will always match.
If ADDREN is set to one, ADDRMASK can be loaded with a second slave address in addition to
the ADDR register. In this mode, the slave will match on two unique addresses, one in ADDR
and the other in ADDRMASK.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x05
Read/Write
Initial Value
–
ADDRMASK[7:1]: Address Mask
R/W
R/W
7
0
7
0
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
ADDRMASK[7:1]
R/W
R/W
4
0
4
0
DATA[7:0]
R/W
R/W
3
0
3
0
Atmel AVR XMEGA B
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
ADDREN
R/W
R/W
0
0
0
0
ADDRMASK
DATA
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