ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 31

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

4.15.4
8291A–AVR–10/11
FUSEBYTE4 – Fuse Byte 4
• Bit 7:5 – Reserved
These fuse bits are reserved. For compatibility with future devices, always write these bits to one
when this register is written.
• Bit: 4 – RSTDISBL: External Reset Disable
This fuse can be programmed to disable the external reset pin functionality. When this is done
pulling th pin low will not cause an external reset. A reset is required before this bit will be read
correctly after it is changed.
• Bit 3:2 – STARTUPTIME[1:0]: Start-up time
These fuse bits can be used to set at a programmable timeout period from all reset sources are
released until the internal reset is released from the delay counter. A reset is required before
these bits will be read correctly after they are changed.
The delay is timed from the 1kHz output of the ULP oscillator. Refer to
page 106
Table 4-4.
• Bit 1 – WDLOCK: Watchdog Timer Lock
The WDLOCK fuse can be programmed to lock the watchdog timer configuration. When this
fuse is programmed the watchdog timer configuration cannot be changed, and the ENABLE bit
in the watchdog CTRL register is automatically set at reset and cannot be cleared from the appli-
cation software. The WEN bit in the watchdog WINCTRL register is not set automatically and
needs to be set from software. A reset is required before this bit will be read correctly after it is
changed.
Table 4-5.
• Bit 0 – JTAGEN: JTAG Enabled
This fuse controls whether or not the JTAG interface is enabled.
When the JTAG interface is disabled all access through JTAG is prohibited, and the device can
be accessed using the program and debug interface (PDI). The JTAGEN fuse is available on
Bit
+0x04
Read/Write
Initial Value
STARTUPTIME[1:0]
WDLOCK
00
01
10
11
for details.
0
1
R/W
7
–
1
Start-up time.
Watchdog timer lock.
R/W
6
–
1
Description
Watchdog timer locked for modifications
Watchdog timer not locked
R/W
5
–
1
RSTDISBL
R/W
4
1
1kHz ULP Oscillator Cycles
STARTUPTIME[1:0]
R/W
3
1
Reserved
Atmel AVR XMEGA B
64
R/W
4
0
2
1
WDLOCK
R/W
1
1
”Reset Sequence” on
JTAGEN
R/W
0
0
FUSEBYTE4
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