ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 242

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.3.8
8291A–AVR–10/11
Arbitration
Three types of clock stretching can be defined, as shown in
Figure 19-8. Clock stretching
Note:
If a slave device is in sleep mode and a START condition is detected, the clock stretching nor-
mally works during the wake-up period. For AVR XMEGA devices, the clock stretching will be
either directly before or after the ACK/NACK bit, as AVR XMEGA devices do not need to wake
up for transactions that are not addressed to it.
A slave device can slow down the bus frequency by stretching the clock periodically on a bit
level. This allows the slave to run at a lower system clock frequency. However, the overall per-
formance of the bus will be reduced accordingly. Both the master and slave device can
randomly stretch the clock on a byte level basis before and after the ACK/NACK bit. This pro-
vides time to process incoming or prepare outgoing data, or perform other time-critical tasks.
In the case where the slave is stretching the clock, the master will be forced into a wait state until
the slave is ready, and vice versa.
A master can start a bus transaction only if it has detected that the bus is idle. As the TWI bus is
a multi-master bus, it is possible that two devices may initiate a transaction at the same time.
This results in multiple masters owning the bus simultaneously. This is solved using an arbitra-
tion scheme where the master loses control of the bus if it is not able to transmit a high level on
the SDA line. The masters who lose arbitration must then wait until the bus becomes idle (i.e.,
wait for a STOP condition) before attempting to reacquire bus ownership. Slave devices are not
involved in the arbitration procedure.
Figure 19-9. TWI arbitration.
SDA
SCL
DEVICE1_SDA
DEVICE2_SDA
SDA
(wired-AND)
SCL
1. Clock stretching is not supported by all I
S
Wakeup clock
stretching
bit 7
S
(1)
.
bit 6
DEVICE1 Loses arbitration
Periodic clock
bit 7
stretching
2
C slaves and masters.
Atmel AVR XMEGA B
bit 6
Figure
bit 0
19-8.
bit 5
ACK/NACK
Random clock
stretching
bit 4
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