ATxmega128B1 Atmel Corporation, ATxmega128B1 Datasheet - Page 62

• Manufacturer Part Number: ATxmega128B1
• Manufacturer: Atmel Corporation

Specifications of ATxmega128B1

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 53
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 10
• Input Capture Channels: 10
• Pwm Channels: 10
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.14.6
5.14.7
8291A–AVR–10/11
TRFCNTH – Block Transfer Count Register H
REPCNT – Repeat Counter Register
byte read by the DMA channel. When TRFCNT reaches zero, the register is reloaded with the
last value written to it.
• Bit 7:0 – TRFCNT[7:0]: Block Transfer Count Register Low byte
These bits hold the LSB of the 16-bit block transfer count.
The default value of this register is 0x1. If a user writes 0x0 to this register and fires a DMA trig-
ger, DMA will be doing 0xFFFF transfers.
Reading and writing 16-bit values requires special attention. For details, refer to
bit Registers” on page
• Bit 7:0 – TRFCNT[15:8]: Block Transfer Count Register High byte
These bits hold the MSB of the 16-bit block transfer count.
The default value of this register is 0x1. If a user writes 0x0 to this register and fires a DMA trig-
ger, DMA will be doing 0xFFFF transfers.
REPCNT counts how many times a block transfer is performed. For each block transfer, this reg-
ister will be decremented.
When repeat mode is enabled (see REPEAT bit in
page
mented after each block transfer if the DMA has to serve a limited number of repeated block
transfers. When repeat mode is enabled, the channel is disabled when REPCNT reaches zero
and the last block transfer is completed. Unlimited repeat is achieved by setting this register to
zero.
Bit
+0x05
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
Bit
+0x04
Read/Write
Initial Value
58), this register is used to control when the transaction is complete. The counter is decre-
R/W
R/W
R/W
7
0
7
1
7
0
12.
R/W
R/W
R/W
6
1
6
0
6
0
R/W
R/W
R/W
5
1
5
0
5
0
R/W
R/W
R/W
4
1
4
0
4
0
TRFCNT[15:8]
TRFCNT[7:0]
REPCNT[7:0]
R/W
R/W
”ADDRCTRL – Address Control Register” on
R/W
3
1
3
0
3
0
Atmel AVR XMEGA B
R/W
R/W
R/W
2
1
2
0
2
0
R/W
R/W
R/W
1
1
1
0
1
0
R/W
R/W
R/W
0
1
0
0
0
0
”Accessing 16-
TRFCNTL
TRFCNTH
REPCNT
62