ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 103
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ATxmega256A3
Manufacturer Part Number
ATxmega256A3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega256A3
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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ATxmega256A3-AU
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20 000
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Part Number:
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20 000
Company:
Part Number:
ATxmega256A3BU-AU
Manufacturer:
ST
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12 000
Company:
Part Number:
ATxmega256A3BU-MH
Manufacturer:
AAT
Quantity:
400
Company:
Part Number:
ATxmega256A3U-AU
Manufacturer:
TI
Quantity:
12 000
Part Number:
ATxmega256A3U-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega256A3U-MH
Manufacturer:
PANASONIC
Quantity:
1 450
8068T–AVR–12/10
11. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
12.
13. DAC refresh may be blocked in S/H mode
14. Conversion lost on DAC channel B in event triggered mode
15. EEPROM page buffer always written when NVM DATA0 is written
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
Using the DAC with a reference voltage above 2.4V or VCC - 0.6V will give inaccurate out-
put when converting codes that give below 0.75V output:
– ±10 LSB for continuous mode
– ±200 LSB for Sample and Hold mode
Problem fix/Workaround
None.
DAC has increased INL or noise for some operating conditions
Some DAC configurations or operating condition will result in increased output error.
– Continous mode: ±5 LSB
– Sample and hold mode: ±15 LSB
– Sample and hold mode for reference above 2.0v: up to ±100 LSB
Problem fix/Workaround
None.
If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is
done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this
will block refresh signals to the second channel.
Problem fix/Workaround
When using the DAC in S/H mode, ensure that none of the channels is running at maximum
conversion rate, or ensure that the conversion rate of both channels is high enough to not
require refresh.
If during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1
conversions are occasionally lost. This means that not all data-values written to the
Channel 1 data register are converted.
Problem fix/Workaround
Keep the DAC conversion interval in the range 000-001 (1 and 3 CLK), and limit the Periph-
eral clock frequency so the conversion internal never is shorter than 1.5 µs.
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM
page buffer.
Problem fix/Workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer
write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM
DATA0 when EELOAD is set.
XMEGA A3
103