ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 27
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ATxmega256A3
Manufacturer Part Number
ATxmega256A3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega256A3
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATxmega256A3-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATxmega256A3-AUR
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
ATxmega256A3B-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega256A3BU-AU
Manufacturer:
ST
Quantity:
12 000
Company:
Part Number:
ATxmega256A3BU-MH
Manufacturer:
AAT
Quantity:
400
Company:
Part Number:
ATxmega256A3U-AU
Manufacturer:
TI
Quantity:
12 000
Part Number:
ATxmega256A3U-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega256A3U-MH
Manufacturer:
PANASONIC
Quantity:
1 450
15. I/O Ports
15.1
15.2
15.3
8068T–AVR–12/10
Features
Overview
I/O configuration
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The XMEGA A3 devices have flexible General Purpose I/O Ports. A port consists of up to 8 pins,
ranging from pin 0 to pin 7. The ports implement several functions, including synchronous/asyn-
chronous input sensing, pin change interrupts and configurable output settings. All functions are
individual per pin, but several pins may be configured in a single operation.
All port pins (Pn) have programmable output configuration. In addition, all port pins have an
inverted I/O function. For an input, this means inverting the signal between the port pin and the
pin register. For an output, this means inverting the output signal between the port register and
the port pin. The inverted I/O function can be used also when the pin is used for alternate
functions.
Selectable input and output configuration for each pin individually
Flexible pin configuration through dedicated Pin Configuration Register
Synchronous and/or asynchronous input sensing with port interrupts and events
Asynchronous wake-up from all input sensing configurations
Two port interrupts with flexible pin masking
Highly configurable output driver and pull settings:
Configuration of multiple pins in a single operation
Read-Modify-Write (RMW) support
Toggle/clear/set registers for Output and Direction registers
Clock output on port pin
Event Channel 0 output on port pin 7
Mapping of port registers (virtual ports) into bit accessible I/O memory space
– Sense both edges
– Sense rising edges
– Sense falling edges
– Sense low level
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Totem-pole
Pull-up/-down
Wired-AND
Wired-OR
Bus-keeper
Inverted I/O
XMEGA A3
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