ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 274

• Manufacturer Part Number: ATxmega256A3
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Speed: No
• Usb Interface: No
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.8.1
24.8.2
24.8.3
8077H–AVR–12/09
Supported Commands
3-Port EBI Configuration
4-Port EBI Configuration
The SDRAM commands that are supported by the EBI is listed in
Table 24-3.
When 3 EBI ports are available, SDRAM can be connected with 3-Port EBI configuration. When
this is done only 4-bit data bus is available, and any chip select must be controlled from software
using a general purpose I/O pin (Pxn).
Figure 24-8. 3-Port SDRAM configuration
When 4 EBI ports are available, SDRAM can be connected with 3-Port or 4-Port EBI configura-
tion. When 4-Port configuration is used, 8-bit data bus is available and all four chip selects will
be available.
Command
NOP
ACTIVE
READ
WRITE
PRECHARGE
AUTO REFRESH
LOAD MODE
SELF REFRESH
Supported SDRAM commands
EBI
Description
No Operation
Activate the selected bank and select the row.
Input the starting column address and begin the burst read operation.
Input the starting column address and begin the burst write operation.
Deactivate the open row of selected bank or all banks
Refresh one row of each bank
Activate self refresh mode
CAS/RE
BA[1:0]
A[11:8]
A[7:0]]
D[3:0]
DQM
CKE
RAS
CLK
Pxn
WE
CLK
CKE
BA[1:0]
DQM
WE
RAS
CAS
D[3:0]
A[7:0]
A[11:8]
CS
Table 24-3 on page
SDRAM
XMEGA A
274.
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