ATxmega256A3 Atmel Corporation, ATxmega256A3 Datasheet - Page 286
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ATxmega256A3
Manufacturer Part Number
ATxmega256A3
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega256A3
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Speed
No
Usb Interface
No
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
16
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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24.12.3
24.12.4
8077H–AVR–12/09
CTRLB (SDRAM) - Chip Select Control Register B
BASEADDR - Chip Select Base Address Register
Table 24-19. Wait State selection (Continued)
This configuration options in this register depend on the Chip Select Mode configuration. The
register description below is valid when the Chip Select Mode is configured for SDRAM
• Bit 7 - SDINITDONE: SDRAM Initialization Complete
This flag is set at the end of the SDRAM initialization sequence. The flag will remain set as long
as the EBI is enabled and the Chip Select is configured for SDRAM.
• Bit 6:3 - Reserved
These bits are reserved and will always be read as zero.
• Bit 2 - SDSREN: SDRAM Self-refresh Enable
When this bit is written to one the EBI controller will send a Self-refresh command to the
SDRAM. For leaving the self refresh mode, the bit must be written to zero.
• Bit 1:0 SDMODE[1:0]: SDRAM Mode
These bits select mode when accessing the SDRAM according to
Table 24-20. SDRAM Mode
Bit
+0x01
Read/Write
Initial Value
Bit
+0x02
+0x03
Read/Write
Initial Value
SRMODE[1:0]
SRWS[2:0]
00
01
10
11
101
110
111
SDINITDONE
R/W
R/W
15
7
0
0
R/W
7
0
NORMAL
LOAD
-
-
Group Configuration
BASEADDR[15:12]
R/W
R/W
14
6
0
0
Group Configuration
5CLK
6CLK
7CLK
R/W
6
0
-
R/W
R/W
13
5
0
0
R/W
5
0
-
BASEADDR[23:16]
R/W
R/W
12
4
0
0
Normal Mode. Access to the SDRAM is decoded normally.
Load Mode. The EBI issues a “Load Mode Register”
command when the SDRAM is accessed.
Reserved
Reserved
Description
R/W
4
0
-
Description
5 CLK
6 CLK
7 CLK
R/W
R/W
11
3
0
0
-
PER2
PER2
PER2
R/W
3
0
-
cycles wait state
cycles wait state
cycles wait state
R/W
R/W
10
2
0
0
-
SDREN
R/W
2
0
Table 24-20 on page
R/W
R/W
1
9
0
0
-
R/W
SDMODE[1:0]
1
0
R/W
R/W
0
8
0
0
-
XMEGA A
R/W
0
0
BASEADDRL
BASEADDRH
.
CTRLB
286.
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