ATxmega64A3U Atmel Corporation, ATxmega64A3U Datasheet - Page 143

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ATxmega64A3U

Manufacturer Part Number
ATxmega64A3U
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega64A3U

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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13.3.4
13.4
8331A–AVR–07/11
Reading the Pin Value
Wired-AND
Figure 13-6. Output configuration - Wired-OR with optional pull-down.
In the wired-AND configuration, the pin will be driven low when the corresponding bits in the
OUT and DIR registers are written to zero. When the OUT register is set to one, the pin is
released allowing the pin to be pulled high with the internal or an external pull-resistor. If internal
pull-up is used, this is also active if the pin is set as input.
Figure 13-7. Output configuration - Wired-AND with optional pull-up.
Independent of the pin data direction, the pin value can be read from the IN register, as shown in
Figure 13-1 on page
register bit and the preceding flip-flop constitute a synchronizer. The synchronizer introduces a
delay on the internal signal line.
chronization when reading an externally applied pin value. The maximum and minimum
propagation delays are denoted as t
140. If the digital input is disabled, the pin value cannot be read. The IN
OUTn
OUTn
INn
INn
Figure 13-8 on page 144
pd,max
and t
pd,min
, respectively.
Atmel AVR XMEGA AU
shows a timing diagram of the syn-
Pn
Pn
143

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