ATxmega64A3U Atmel Corporation, ATxmega64A3U Datasheet - Page 8
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ATxmega64A3U
Manufacturer Part Number
ATxmega64A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A3U
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A3U-AU
Manufacturer:
ACTEL
Quantity:
101
Part Number:
ATxmega64A3U-MH
Manufacturer:
TI/德州仪器
Quantity:
20 000
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3.4.1
3.5
3.6
8331A–AVR–07/11
Program Flow
Instruction Execution Timing
Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware mul-
tiplier supports different variations of signed and unsigned integer and fractional numbers:
A multiplication takes two CPU clock cycles.
After reset, the CPU starts to execute instructions from the lowest address in the flash program-
memory ‘0.’ The program counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of
addressing the whole address space directly. Most AVR instructions use a 16-bit word format,
while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is
allocated in the general data SRAM, and consequently the stack size is only limited by the total
SRAM size and the usage of the SRAM. After reset, the stack pointer (SP) points to the highest
address in the internal SRAM. The SP is read/write accessible in the I/O memory space,
enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
The AVR CPU is clocked by the CPU clock, clk
on page 8
vard architecture and the fast-access register file concept. This is the basic pipelining concept
used to obtain up to 1MIPS/MHz performance with high power efficiency.
Figure 3-2.
• Multiplication of unsigned integers
• Multiplication of signed integers
• Multiplication of a signed integer with an unsigned integer
• Multiplication of unsigned fractional numbers
• Multiplication of signed fractional numbers
• Multiplication of a signed fractional number with an unsigned one
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
shows the parallel instruction fetches and instruction executions enabled by the Har-
The parallel instruction fetches and instruction executions.
clk
CPU
T1
CPU
. No internal clock division is used.
Atmel AVR XMEGA AU
T2
T3
T4
Figure 3-2
8
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