ATxmega64A3U Atmel Corporation, ATxmega64A3U Datasheet - Page 246

• Manufacturer Part Number: ATxmega64A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3U

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.13.3
8331A–AVR–07/11
STATUS – Status Register
• Bit 4 – PULLRST: Pull during Reset
Setting this bit enables the pull-up on the USB bus to be held also when the device enters reset.
The bit will be cleared on Power-On Reset.
• Bit 3 – Reserved
This bit is reserved for future use. For compatibility with future devices, always write this bit to
zero when this register is written.
• Bit 2 – RWAKEUP: Remote Wake-up
Setting this bit sends an upstream resume on the USB bus if the USB bus is in the suspend
state for at least 5 ms.
• Bit 1 – GNACK: Global NACK
When this bit is set, the USB module will NACK all incoming transactions. Expect for SETUP
packet, this prevents the USB module from performing any on-chip SRAM access, giving all
SRAM bandwidth to the CPU and/or DMA Controller.
• Bit 0 – ATTACH: Attach
Setting this bit enables the internal D+ or D- pull up (depending on the USB speed selection),
and attaches the device to the USB lines. Clearing this bit disconnects the device from the USB
lines.
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3 – URESUME: Upstream Resume
This flag is set when an upstream resume is sent.
• Bit 2 – RESUME: Resume
This flag is set when a downstream resume is received.
• Bit 1 – SUSPEND: Bus Suspended
This flag is set when the USB bus is in the suspended state (the bus has been idle for at least
3ms).
• Bit 0 – BUSRST: Bus Reset
This flag is set when a reset condition has been detected (the bus has been driven to SE0 for at
least 2.5µs).
Bit
+0x02
Read/Write
Initial Value
7
–
R
0
R
6
–
0
R
5
–
0
R
4
–
0
URESUME
Atmel AVR XMEGA AU
R
3
0
RESUME
R
2
0
SUSPEND
R
1
0
BUSRST
R
0
0
STATUS
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