R40008 Atmel Corporation, R40008 Datasheet - Page 171
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R40008
Manufacturer Part Number
R40008
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.R40008.pdf
(19 pages)
4.R40008.pdf
(20 pages)
Specifications of R40008
Flash (kbytes)
0 Kbytes
Pin Count
100
Max. Operating Frequency
75 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
256
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
No
Calibrated Rc Oscillator
No
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6.20
ARM DDI 0029G
Instruction speed summary
Due to the pipelined architecture of the CPU, instructions overlap considerably. In a
typical cycle, one instruction can be using the data path while the next is being decoded
and the one after that is being fetched. For this reason Table 6-23 presents the
incremental number of cycles required by an instruction, rather than the total number of
cycles for which the instruction uses part of the processor. Elapsed time, in cycles, for
a routine can be calculated from these figures listed in Table 6-23. These figures assume
that the instruction is actually executed. Unexecuted instructions take one cycle.
If the condition is not met then all instructions take one S-cycle. The cycle types N, S,
I, and C are described in Bus cycle types on page 3-4.
In Table 6-23:
•
•
•
b is the number of cycles spent in the coprocessor busy-wait loop
m is:
—
—
—
n is the number of words transferred.
Copyright © 1994-2001. All rights reserved.
1 if bits [32:8] of the multiplier operand are all zero or one
2 if bits [32:16] of the multiplier operand are all zero or one
3 if bits [31:24] of the multiplier operand are all zero or all one
Instruction
Data Processing
MSR, MRS
LDR
STR
LDM
STM
SWP
B,BL
SWI, trap
MUL
MLA
Table 6-23 ARM instruction speed summary
Cycle count
S
S
S+N+I
2N
nS+N+I
(n-1)S+2N
S+2N+I
2S+N
2S+N
S+mI
S+(m+1)I
Instruction Cycle Timings
Additional
+I for SHIFT(Rs)
+S + N if R15 written
-
+S +N if R15 loaded
-
+S +N if R15 loaded
-
-
-
-
-
-
6-29
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