R40008 Atmel Corporation, R40008 Datasheet - Page 81
R40008
Manufacturer Part Number
R40008
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.R40008.pdf
(19 pages)
4.R40008.pdf
(20 pages)
Specifications of R40008
Flash (kbytes)
0 Kbytes
Pin Count
100
Max. Operating Frequency
75 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
256
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
No
Calibrated Rc Oscillator
No
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3.4
3.4.1
3.4.2
3.4.3
ARM DDI 0029G
Addressing signals
A[31:0]
nRW
MAS[1:0]
The address class signals are:
•
•
•
•
•
•
•
A[31:0] is the 32-bit address bus that specifies the address for the transfer. All addresses
are byte addresses, so a burst of word accesses results in the address bus incrementing
by four for each cycle.
The address bus provides 4GB of linear addressing space.
When a word access is signaled the memory system ignores the bottom two bits, A[1:0],
and when a halfword access is signaled the memory system ignores the bottom bit,
A[0].
All data values must be aligned on their natural boundaries. All words must be
word-aligned.
nRW specifies the direction of the transfer. nRW indicates an ARM7TDMI processor
write cycle when HIGH, and an ARM7TDMI processor read cycle when LOW. A burst
of S-cycles is always either a read burst, or a write burst. The direction cannot be
changed in the middle of a burst.
The MAS[1:0] bus encodes the size of the transfer. The ARM7TDMI processor can
transfer word, halfword, and byte quantities.
All writable memory in an ARM7TDMI processor based system must support the
writing of individual bytes or halfwords to allow the use of the C Compiler and the
ARM debug tool chain, for example Multi-ICE.
A[31:0] on page 3-11
nRW on page 3-11
MAS[1:0] on page 3-11
nOPC on page 3-12
nTRANS on page 3-13
LOCK on page 3-13
TBIT on page 3-13.
Copyright © 1994-2001. All rights reserved.
Memory Interface
3-11
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