SAM3N1C Atmel Corporation, SAM3N1C Datasheet - Page 141

• Manufacturer Part Number: SAM3N1C
• Manufacturer: Atmel Corporation

Specifications of SAM3N1C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.18.4
10.18.4.1
10.18.4.2
10.18.4.3
10.18.4.4
11011A–ATARM–04-Oct-10
DSB ; Data Synchronisation Barrier
DSB
Syntax
Operation
Condition flags
Examples
Data Synchronization Barrier.
where:
cond
DSB acts as a special data synchronization memory barrier. Instructions that come after the
DSB, in program order, do not execute until the DSB instruction completes. The DSB instruction
completes when all explicit memory accesses before it complete.
This instruction does not change the flags.
DSB{cond}
is an optional condition code, see
“Conditional execution” on page
84.
SAM3N
141