SAM3N1C Atmel Corporation, SAM3N1C Datasheet - Page 559
SAM3N1C
Manufacturer Part Number
SAM3N1C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N1C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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• RSTSTA: Reset Status Bits
0: No effect.
1: Resets the status bits PARE, FRAME, OVRE, UNRE and RXBRK in US_CSR.
• STTBRK: Start Break
0: No effect.
1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been trans-
mitted. No effect if a break is already being transmitted.
• STPBRK: Stop Break
0: No effect.
1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.
No effect if no break is being transmitted.
• STTTO: Start Time-out
0: No effect.
1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR.
• SENDA: Send Address
0: No effect.
1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set.
• RSTIT: Reset Iterations
0: No effect.
1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled.
• RSTNACK: Reset Non Acknowledge
0: No effect
1: Resets NACK in US_CSR.
• RETTO: Rearm Time-out
0: No effect
1: Restart Time-out
• RTSEN: Request to Send Enable
0: No effect.
1: Drives the pin RTS to 0.
• FCS: Force SPI Chip Select
FCS = 0: No effect.
FCS = 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave
devices supporting the CSAAT Mode (Chip Select Active After Transfer).
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
– Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE):
SAM3N
SAM3N
559
559
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