SAM3N2A Atmel Corporation, SAM3N2A Datasheet - Page 319
SAM3N2A
Manufacturer Part Number
SAM3N2A
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N2A
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
47
Ext Interrupts
47
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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22. Peripheral DMA Controller (PDC)
22.1
22.2
11011A–ATARM–04-Oct-10
Description
Embedded Characteristics
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the
on- and/or off-chip memories. The link between the PDC and a serial peripheral is operated by
the AHB to ABP bridge.
The user interface of each PDC channel is integrated into the user interface of the peripheral it
serves. The user interface of mono directional channels (receive only or transmit only), contains
two 32-bit memory pointers and two 16-bit counters, one set (pointer, counter) for current trans-
fer and one set (pointer, counter) for next transfer. The bi-directional channel user interface
contains four 32-bit memory pointers and four 16-bit counters. Each set (pointer, counter) is
used by current transmit, next transmit, current receive and next receive.
Using the PDC removes processor overhead by reducing its intervention during the transfer.
This significantly reduces the number of clock cycles required for a data transfer, which
improves microcontroller performance.
To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and
receive signals. When the programmed data is transferred, an end of transfer interrupt is gener-
ated by the peripheral itself.
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 22-1.
Instance name
• Handles data transfer between peripherals and memories
• Low bus arbitration overhead
• Next Pointer management for reducing interrupt latency requirement
USART0
USART0
UART0
UART0
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
TWI0
TWI0
ADC
DAC
SPI
SPI
Peripheral DMA Controller
Channel T/R
Transmit
Transmit
Transmit
Transmit
Transmit
Receive
Receive
Receive
Receive
Receive
100 & 64 Pins
x
x
x
x
x
x
x
x
x
x
48 Pins
N/A
x
x
x
x
x
x
x
x
x
SAM3N
319
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