SAM3S1C Atmel Corporation, SAM3S1C Datasheet - Page 225
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SAM3S1C
Manufacturer Part Number
SAM3S1C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S1C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
39
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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12.3.3
12.3.4
12.3.4.1
Figure 12-3. General Reset State
6500C–ATARM–8-Feb-11
backup_nreset
periph_nreset
proc_nreset
(nrst_out)
RSTTYP
SLCK
NRST
MCK
Brownout Manager
Reset States
General Reset
As the ERSTL field is within RSTC_MR register, which is backed-up, it can be used to shape the
system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator.
The Brownout manager is embedded within the Supply Controller, please refer to the product
Supply Controller section for a detailed description.
The Reset State Manager handles the different reset sources and generates the internal reset
signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The
update of the field RSTTYP is performed when the processor reset is released.
A general reset occurs when a Power-on-reset is detected, a Brownout or a Voltage regulation
loss is detected by the Supply controller. The vddcore_nreset signal is asserted by the Supply
Controller when a general reset occurs.
All the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset.
As the RSTC_MR is reset, the NRST line rises 2 cycles after the vddcore_nreset, as ERSTL
defaults at value 0x0.
Figure 12-3
shows how the General Reset affects the reset signals.
XXX
EXTERNAL RESET LENGTH
= 2 cycles
Processor Startup
= 2 cycles
0x0 = General Reset
Freq.
Any
SAM3S
XXX
225
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