SAM7SE512 Atmel Corporation, SAM7SE512 Datasheet - Page 173
SAM7SE512
Manufacturer Part Number
SAM7SE512
Description
Manufacturer
Atmel Corporation
Specifications of SAM7SE512
Flash (kbytes)
512 Kbytes
Pin Count
144
Max. Operating Frequency
48 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
88
Ext Interrupts
88
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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22.6.4.5
6222F–ATARM–14-Jan-11
Early Read Wait State
Figure 22-17. Chip Select Wait State
Notes:
In early read protocol, an early read wait state is automatically inserted when an external write
cycle is followed by a read cycle to allow time for the write cycle to end before the subsequent
read cycle begins (see
grammed wait states (i.e., data float wait state).
No wait state is added when a read cycle is followed by a write cycle, between consecutive
accesses of the same type, or between external and internal memory accesses.
Figure 22-18. Early Read Wait States
1. Early Read Protocol
2. Standard Read Protocol
A[22:0]
D[15:0]
NWE
MCK
A[22:0]
NCS1
NCS2
NRD
NWE
MCK
NRD
NCS
Figure
(1)
Write Cycle
addr Mem 1
22-18). This wait state is generated in addition to any other pro-
Mem 1
(2)
Early Read Wait
Chip Select Wait
addr Mem 2
SAM7SE512/256/32
Read Cycle
Mem 2
173
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