SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 135

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

TC Channel Mode Register: Capture Mode
Register Name: TC_CMR
Access Type:
Reset Value:
Offset:
• TCCLKS: Clock Selection
• CLKI: Clock Invert (Code Label TC_CLKI)
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
• LDBSTOP: Counter Clock Stopped with RB Loading (Code Label TC_LDBSTOP)
0 = Counter clock is not stopped when RB loading occurs.
1 = Counter clock is stopped when RB loading occurs.
1354D–ATARM–08/02
WAVE = 0
0
0
1
1
LDBDIS
0
0
0
0
1
1
1
1
BURST
31
23
15
–
–
7
TCCLKS
0
1
0
1
0
0
1
1
0
0
1
1
Read/Write
0
0x04
LDBSTOP
Selected BURST
The clock is not gated by an external signal
XC0 is ANDed with the selected clock
XC1 is ANDed with the selected clock
XC2 is ANDed with the selected clock
CPCTRG
30
22
14
–
–
6
0
1
0
1
0
1
0
1
Clock Selected
MCK/2
MCK/8
MCK/32
MCK/128
MCK/1024
XC0
XC1
XC2
29
21
13
–
–
–
5
BURST
28
20
12
–
–
–
4
CLKI
27
19
11
–
–
3
LDRB
ABETRG
26
18
10
–
2
TC_CLKS_MCK1024
TC_CLKS_MCK128
TC_CLKS_MCK32
AT91X40 Series
TC_BURST_NONE
TC_CLKS_MCK2
TC_CLKS_MCK8
TC_BURST_XC0
TC_BURST_XC1
TC_BURST_XC2
TC_CLKS_XC0
TC_CLKS_XC1
TC_CLKS_XC2
Code Label
Code Label
TC_BURST
TC_CLKS
TCCLKS
25
17
–
9
1
ETRGEDG
LDRA
24
16
–
8
0
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