SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 52
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SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G15 PDF datasheet #4
- SAM9G15 PDF datasheet #5
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- Download datasheet (30Mb)
10.6
10.6.1
10.6.2
10.6.3
52
52
Functional Description
SAM9G35
SAM9G35
Test Pin
EmbeddedICE
JTAG Signal Description
™
One dedicated pin, TST, is used to define the device operating mode. The user must make sure
that this pin is tied at low level to ensure normal operating conditions. Other values associated
with this pin are reserved for manufacturing test.
The ARM9EJ-S EmbeddedICE-RT
host computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core
embedded within the ARM926EJ-S. The internal state of the ARM926EJ-S is examined through
an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core
without using the external data bus. Therefore, when in debug state, a store-multiple (STM) can
be inserted into the instruction pipeline. This exports the contents of the ARM9EJ-S registers.
This data can be serially shifted out without affecting the rest of the system.
There are two scan chains inside the ARM9EJ-S processor which support testing, debugging,
and programming of the EmbeddedICE-RT. The scan chains are controlled by the ICE/JTAG
port.
EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly
between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed.
For further details on the EmbeddedICE-RT, see the ARM document:
ARM9EJ-S Technical Reference Manual (DDI 0222A).
TMS is the Test Mode Select input which controls the transitions of the test interface state
machine.
TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan
Register, Instruction Register, or other data registers).
TDO is the Test Data Output line which is used to serially output the data from the JTAG regis-
ters to the equipment controlling the test. It carries the sampled values from the boundary scan
chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit.
NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM
cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a
Power On Reset output. It is asserted on power on. If necessary, the user can also reset the
debug logic with the NTRST pin assertion during 2.5 MCK periods.
TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment
controlling the test and not by the tested device. It can be pulsed at any frequency. Note the
maximum JTAG clock rate on ARM926EJ-S cores is 1/6th the clock of the CPU. This gives 5.45
kHz maximum initial JTAG clock rate for an ARM9E running from the 32.768 kHz slow clock.
RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock
handling by emulators. From some ICE Interface probes, this return signal can be used to syn-
chronize the TCK clock and take not care about the given ratio between the ICE Interface clock
and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in
boundary scan mode.
™
is supported via the ICE/JTAG port. It is connected to a
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
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