SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 11
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SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G15 PDF datasheet #4
- SAM9G15 PDF datasheet #5
- Current page: 11 of 248
- Download datasheet (2Mb)
List of Figures
ARM926EJ-S Technical Reference Manual
ARM DDI0198D
Figure 1-1
Figure 1-2
Figure 1-3
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 2-7
Figure 2-8
Figure 2-9
Figure 2-10
Figure 2-11
Figure 2-12
Figure 2-13
Figure 2-14
Figure 2-15
Figure 2-16
Figure 3-1
Figure 3-2
Figure 3-3
Key to timing diagram conventions ............................................................................ xix
ARM926EJ-S block diagram ..................................................................................... 1-3
ARM926EJ-S interface diagram (part one) ............................................................... 1-4
ARM926EJ-S interface diagram (part two) ............................................................... 1-5
CP15 MRC and MCR bit pattern ............................................................................... 2-5
Cache Type Register format ..................................................................................... 2-9
Dsize and Isize field format ....................................................................................... 2-9
TCM Status Register format .................................................................................... 2-12
Control Register format ........................................................................................... 2-13
TTBR format ............................................................................................................ 2-17
Register c3 format ................................................................................................... 2-18
FSR format .............................................................................................................. 2-19
Register c7 MVA format .......................................................................................... 2-23
Register c7 Set/Way format .................................................................................... 2-24
Register c8 MVA format .......................................................................................... 2-26
Cache Lockdown Register c9 format ...................................................................... 2-27
TCM Region Register c9 format .............................................................................. 2-30
TLB Lockdown Register format ............................................................................... 2-32
Process ID Register format ..................................................................................... 2-34
Context ID Register format ...................................................................................... 2-35
Translation Table Base Register ............................................................................... 3-6
Translating page tables ............................................................................................. 3-7
Accessing translation table first-level descriptors ...................................................... 3-8
Copyright © 2001-2003 ARM Limited. All rights reserved.
xi
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