SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 17
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SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G15 PDF datasheet #4
- SAM9G15 PDF datasheet #5
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ARM DDI0198D
Chapter 6 Bus Interface Unit
Chapter 7 Noncachable Instruction Fetches
Chapter 8 Coprocessor Interface
Chapter 9 Instruction Memory Barrier
Chapter 10 Embedded Trace Macrocell Support
Chapter 11 Debug Support
Chapter 12 Power Management
Appendix A Signal Descriptions
Appendix B CP15 Test and Debug Registers
Copyright © 2001-2003 ARM Limited. All rights reserved.
Read this chapter for a description of the Bus Interface Unit (BIU)
interface to AMBA.
Read this chapter for a description of how speculative noncachable
instruction fetches are used in the ARM926EJ-S processor to improve
performance.
Read this chapter for a description of the coprocessor interface. The
chapter includes timing diagrams for coprocessor operations.
Read this chapter for the Instruction Memory Barrier (IMB) description
and how IMB operations are used to ensure consistency between data and
instruction streams processed by the ARM926EJ-S processor.
Read this chapter to understand how Embedded Trace Macrocell (ETM)
is supported in the ARM926EJ-S processor.
Read this chapter for a description of the debug interface and
EmbeddedICE-RT.
Read this chapter for a description of the power management facilities
provided by the ARM926EJ-S processor.
This appendix lists the ARM926EJ-S processor signals in functional
groups.
Read this appendix for detailed information on the registers used for test
and debug.
Preface
xvii
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