SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 129

• Manufacturer Part Number: SAM9G20
• Manufacturer: Atmel Corporation

Specifications of SAM9G20

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 7
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 95
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM926EJ-S
5.5.3
ARM DDI0198D
DRADDR[17:0]
DRWD[31:0]
DRWBL[3:0]
DRSIZE[3:0]
DRRD[31:0]
DRWAIT
DRnRW
Multiple banks of RAM example
DRCS
CLK
b0110 DIN[7:0]
The rules for connecting four RAM blocks are:
•
•
In little-endian mode, DRWBL[0] indicates the LSB of the word and DRWBL[3]
indicates the MSB. In big-endian mode, DRWBL[3] indicates the LSB of the word and
DRWBL[0] indicates the MSB.
If you have to create a large memory out of smaller RAM blocks, there are two methods
for doing this:
•
CLK
CS
DRWR[7:0]
32K RAM
Byte 0
A[14:0]
Copyright © 2001-2003 ARM Limited. All rights reserved.
Each byte-wide RAM has the same address and chip-select control as the
word-wide RAM.
The following connections must be made:
—
—
—
—
If minimizing power consumption is more important than a fast design, you must
follow the example in Optimizing for power on page 5-22.
DOUT[7:0]
Note
DRADDR[14:0]
WE
DRWBL[0], DRWD[7:0], and DRRD[7:0], connect to RAM byte 0
DRWBL[1], DRWD[15:8], and DRRD[15:8], connect to RAM byte 1
DRWBL[2], DRWD[23:16], and DRRD[23:16], connect to RAM byte 2
DRWBL[3], DRWD[31:24], and DRRD[31:24], connect to RAM byte 3.
DRRD[7:0]
DRWBL[0]
DIN[7:0]
CLK
CS
DRWR[15:8]
32K RAM
Byte 1
A[14:0]
DOUT[7:0]
WE
DRRD[15:8]
DRWBL[1]
DIN[7:0]
CLK
CS
Figure 5-13 Byte-banks of RAM example
DRWR[23:16]
32K RAM
Byte 2
A[14:0]
DOUT[7:0]
WE
DRRD[23:16]
DRWBL[2]
Tightly-Coupled Memory Interface
DIN[7:0]
CLK
CS
DRWR[31:24]
32K RAM
Byte 3
A[14:0]
DOUT[7:0]
WE
DRRD[31:24]
DRWBL[3]
5-21