SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 210
SAM9G20
Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G20.pdf
(42 pages)
5.SAM9G20.pdf
(832 pages)
Specifications of SAM9G20
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G20 PDF datasheet #4
- SAM9G20 PDF datasheet #5
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- Download datasheet (2Mb)
CP15 Test and Debug Registers
B.1.2
B-4
Debug and Test Address Register
Bit 15, disable block-level clock gating
Bit 16, disable NC instruction prefetching
Bits 17 & 18, abort instruction TLB miss
Bit 19, test and clean all
This register defines the address used for debug and test operations, and for MMU test
operations using the MMU Test Register.
You can access the Debug and Test Address Register using the following instructions:
Copyright © 2001-2003 ARM Limited. All rights reserved.
You can use this bit to disable block-level clock gating with the
ARM926EJ-S processor. This bit does not affect the functionality of the
ARM926EJ-S processor. It allows the benefits of block-level clock gating
to be evaluated without the requirement to build two different
implementations of the ARM926EJ-S macrocell, one with block-level
clock gating, one without.
You can use this bit to disable speculative prefetching for instructions in
noncachable areas of memory. The default behavior of ARM926EJ-S
processor is to perform speculative sequential instruction fetches on the
AHB interface. Disabling prefetching prevents any speculative
noncachable instruction prefetches by the ARM926EJ-S memory
system, and only instruction requests issued by the ARM9EJ-S core
result in instruction fetches on the AHB interface.
You can use the abort data TLB miss and abort instruction TLB miss bits
to prevent page table walks occurring as the result of a TLB miss. When
set, a TLB miss results in the access being aborted as if the access has
resulted in a translation fault, and a value of
status field of the appropriate FSR.
You can use the test-and-clean-all bit to modify the behavior of the test
and clean, and test clean and invalidate instructions so that a single
instruction can be used to clean or clean and invalidate the entire cache.
This is only intended for use by a debugger, to provide an efficient way
to clean the data cache using scan chain 15.
being written into the
ARM DDI0198D
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