SAM9G35 Atmel Corporation, SAM9G35 Datasheet - Page 170
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SAM9G35
Manufacturer Part Number
SAM9G35
Description
Manufacturer
Atmel Corporation
Specifications of SAM9G35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Coprocessor Interface
8.10
8-14
Connecting multiple external coprocessors
If multiple coprocessors are connected to the ARM926EJ-S processor, then outputs of
the various coprocessors must be combined to form a single set of coprocessor inputs.
The coprocessor handshake signals are combined together by ANDing the top bit and
ORing the bottom bit. This enables a coprocessor to produce a fixed response of
(Absent), when it is inactive. The other external coprocessor inputs, CPDIN and
CPBURST, are combined by ORing. This is shown in Figure 8-10.
The OR arrangement for CPBURST and CPDIN means that coprocessors must drive
zero values onto their CPBURST and CPDIN outputs when they are inactive, or do not
own the corresponding coprocessor pipeline stage associated with these signals.
Copyright © 2001-2003 ARM Limited. All rights reserved.
CPBURST[3:0]
ARM926EJ-S
CHSDE[1:0]
CHSEX[1:0]
CPDIN[3:0]
Figure 8-10 Arrangement for connecting two coprocessors
CHSDE[1]
CHSDE[0]
CHSEX[1]
CHSEX[0]
CHSDEa[1]
CHSDEb[1]
CHSDEa[0]
CHSDEb[0]
CHSEXa[1]
CHSEXb[1]
CHSEXa[0]
CHSEXb[0]
CPBURSTa[3:0]
CPBURSTb[3:0]
CPDINa[3:0]
CPDINb[3:0]
ARM DDI0198D
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