SAM9XE256 Atmel Corporation, SAM9XE256 Datasheet - Page 92

• Manufacturer Part Number: SAM9XE256
• Manufacturer: Atmel Corporation

Specifications of SAM9XE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

14.2.5.6
14.2.5.7
92
AT91SAM9XE128/256/512 Preliminary
Flash Security Bit Command
Memory Write Command
General-purpose NVM bits can be read using the Get GPNVM Bit command (GGPB). The n
GP NVM bit is active when bit n of the bit mask is set..
Table 14-13. Get GP NVM Bit Command
A security bit can be set using the Set Security Bit command (SSE). Once the security bit is
active, the Fast Flash programming is disabled. No other command can be run. An event on the
Erase pin can erase the security bit once the contents of the Flash have been erased.
Table 14-14. Set Security Bit Command
Once the security bit is set, it is not possible to access FFPI. The only way to erase the security
bit is to erase the Flash.
In order to erase the Flash, the user must perform the following:
Then it is possible to return to FFPI mode and check that Flash is erased.
This command is used to perform a write access to any memory location.
The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking
can be chained; an internal address buffer is automatically increased.
Table 14-15. Write Command
Step
1
2
Step
1
2
Step
1
2
3
4
5
...
n
• Power-off the chip
• Power-on the chip with TST = 0
• Assert Erase during a period of more than 220 ms
• Power-off the chip
Handshake Sequence
Write handshaking
Read handshaking
Handshake Sequence
Write handshaking
Write handshaking
Handshake Sequence
Write handshaking
Write handshaking
Write handshaking
Write handshaking
Write handshaking
...
Write handshaking
MODE[3:0]
CMDE
ADDR0
ADDR1
DATA
DATA
...
ADDR0
MODE[3:0]
CMDE
DATA
MODE[3:0]
CMDE
DATA
DATA[15:0]
WRAM
Memory Address LSB
Memory Address
*Memory Address++
*Memory Address++
...
Memory Address LSB
DATA[15:0]
SSE
0
DATA[15:0]
GGPB
GP NVM Bit Mask Status
0 = GP NVM bit is cleared
1 = GP NVM bit is set
6254C–ATARM–22-Jan-10
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