SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 115
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SAM9XE512
Manufacturer Part Number
SAM9XE512
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE512
Flash (kbytes)
512 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 115 of 290
- Download datasheet (5Mb)
5.3
ARM DDI 0165B
Maximum interrupt latency
The processor samples the interrupt input pins on the rising-edge of the system clock,
CLK. The sampled signal is examined and can cause an interrupt in the following cases:
•
•
•
•
If the sampled signal is asserted at the same time as a multicycle instruction has started
its second or later cycle of execution, the interrupt exception entry does not start until
the instruction has completed.
The worst-case interrupt latency occurs when the longest possible
incurs a Data Abort. The processor must enter the Data Abort mode before taking the
interrupt so that the interrupt exception exit can occur correctly. This causes a
worst-case latency of 24 cycles:
•
•
•
•
•
•
Whenever a new instruction is scheduled to enter the Execute stage of the
pipeline.
Whenever a new instruction is in the Execute stage for the first cycle of its
execution. Here cycle refers to CLK cycles with CLKEN HIGH.
Whenever a coprocessor instruction is being busy waited in the Execute stage.
Whenever a new instruction which interlocked in the Execute stage has just
progressed to its first active Execute cycle.
The longest
Counting the first Execute cycle as 1, the
The last word to be transferred by the
status for the transfer is returned in this cycle.
If a Data Abort happens, the processor detects this in cycle 18 and prepares for
the Data Abort exception entry in cycle 19.
Cycles 20 and 21 are the Fetch and Decode stages of the Data Abort entry
respectively.
During cycle 22, the processor prepares for FIQ entry, issuing Fetch and Decode
cycles in cycles 23 and 24.
Therefore, the first instruction in the FIQ routine enters the Execute stage of the
pipeline in stage 25, giving a worst-case latency of 24 cycles.
Copyright © 2000 ARM Limited. All rights reserved.
LDM
instruction is one that loads all of the registers, including the PC.
LDM
LDM
is transferred in cycle 17, and the abort
takes 16 cycles.
LDM
instruction
Interrupts
5-7
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