SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 62
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SAM9XE512
Manufacturer Part Number
SAM9XE512
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE512
Flash (kbytes)
512 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 62 of 290
- Download datasheet (5Mb)
Programmer’s Model
2.9
2.9.1
2-20
Exception
or entry
SWI
UNDEF
PABT
FIQ
IRQ
DABT
RESET
BKPT
Exceptions
Exception entry and exit summary
Return instruction
MOVS PC, R14_svc
MOVS PC, R14_und
SUBS PC, R14_abt, #4
SUBS PC, R14_fiq, #4
SUBS PC, R14_irq, #4
SUBS PC, R14_abt, #8
NA
SUBS PC, R14_abt, #4
Exceptions arise whenever the normal flow of a program has to be halted temporarily,
for example, to service an interrupt from a peripheral. Before attempting to handle an
exception, the ARM9E-S preserves the current processor state so that the original
program can resume when the handler routine has finished.
If two or more exceptions arise simultaneously, the exceptions are dealt with in the fixed
order given in Exception priorities on page 2-27.
This section provides details of the ARM9E-S exception handling:
•
•
•
Table 2-3 summarizes the PC value preserved in the relevant r14 on exception entry,
and the recommended instruction for exiting the exception handler.
Exception entry and exit summary
Entering an exception on page 2-21
Leaving an exception on page 2-21.
Copyright © 2000 ARM Limited. All rights reserved.
Previous state
ARM r14_x
PC + 4
PC + 4
PC + 4
PC + 4
PC + 4
PC + 8
-
PC + 4
PC+2
PC+4
PC+4
Thumb r14_x
PC+2
PC+4
PC+8
-
PC+4
Table 2-3 Exception entry and exit
Notes
Where the PC is the address of the
SWI, undefined instruction, or
instruction that had the Prefetch
Abort.
Where the PC is the address of the
instruction that was not executed
because the FIQ or IRQ took
priority.
Where the PC is the address of the
Load or Store instruction that
generated the Data Abort.
The value saved in r14_svc upon
reset is UNPREDICTABLE.
Software breakpoint.
ARM DDI 0165B
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