SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 28

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

Table 6-1.
6.2.1
6.3
30
30
SYSTEM_IO
Bit Number
12
Test Pin
SAM3X/A
SAM3X/A
Serial Wire JTAG Debug Port (SWJ-DP) Pins
System I/O Configuration Pin List
Peripheral
A
A
A
A
-
Note:
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on
a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference
and reset state, refer to
At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging
probe. Please refer to the “Debug and Test” section of the product datasheet.
SWJ-DP pins can be used as standard I/Os to provide users with more general input/output pins
when the debug port is not needed in the end application. Mode selection between SWJ-DP
mode (System IO mode) and general IO mode is performed through the AHB Matrix Special
Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, debouncing
and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left uncon-
nected for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial
Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and
TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire
Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous
trace can only be used with SW-DP, not JTAG-DP. For more information about SW-DP and
JTAG-DP switching, please refer to the “Debug and Test” section of the product datasheet.
All JTAG signals are supplied with VDDIO except JTAGSEL, supplied by VDDBU.
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming
mode of the SAM3X/A series. The TST pin integrates a permanent pull-down resistor of about
15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast program-
ming mode, see the “Fast Flash Programming Interface” section. For more information on the
manufacturing and test mode, refer to the “Debug and Test” section of the product datasheet.
TDO/TRACESWO
Default Function
TCK/SWCLK
TMS/SWDIO
After Reset
1. If PC0 is used as PIO input in user applications, a low level must be ensured at startup to pre-
ERASE
vent Flash erase before the user application sets PC0 into PIO mode.
TDI
Table
Other Function
PB28
PB29
PB30
PB31
PC0
3-1.
Constraints for
Normal Start
Low Level at
startup
-
-
-
-
()
Register“ in the “Bus Matrix“ section
(Refer to “System IO Configuration
In Matrix User Interface Registers
of the product datasheet.)
In PIO Controller
Configuration
11057AS–ATARM–10-Feb-12
11057AS–ATARM–10-Feb-12