SAM3X8E Atmel Corporation, SAM3X8E Datasheet
SAM3X8E
Related parts for SAM3X8E
SAM3X8E Summary of contents
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Features • Core ® ® – ARM Cortex -M3 revision 2.0 running MHz – Memory Protection Unit (MPU) ® – Thumb -2 instruction set – 24-bit SysTick Counter – Nested Vector Interrupt Controller • Memories – ...
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... SHDN Pin EMAC External Bus Interface SDRAM Controller Central DMA 12-bit ADC 12-bit DAC SAM3X/A 2 Configuration Summary SAM3X8H SAM3X8E SAM3X8C 2 x 256 2 x 256 Kbytes 2 x 256 Kbytes Kbytes Kbytes Kbytes Kbytes Yes Yes - (1) 4K bytes 4K bytes - LQFP144 ...
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... Number of SPI Controllers / Number of Chip Selects + Number of USART with SPI Mode channels are accessible through PIO channels are accessible through PIO channels are accessible through PIO 7. USART3 in UART mode (RXD3 and TXD3 available) 11057A–ATARM–17-Feb-12 Configuration Summary (Continued) SAM3X8H SAM3X8E SAM3X8C (4) (5) ( ...
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SAM3X/A Block Diagram Figure 2-1. SAM3A4/8C (100 pins) Block Diagram System Controller TST PCK0-PCK2 PLLA UPLL XIN OSC XOUT WDT RC 12/8/4 M FWUP XIN32 XOUT32 ERASE VDDBU VDDCORE VDDUTMI NRST PIOA PIOC TWCK0 TWD0 TWCK1 TWD1 URXD UTXD ...
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Figure 2-2. SAM3X4/8C (100 pins) Block Diagram System Controller TST PCK0-PCK2 PLLA UPLL XIN OSC 12M XOUT WDT RC 12/8/4 M FWUP XIN32 XOUT32 ERASE VDDBU VDDCORE VDDUTMI NRST PIOA PIOC TWCK0 TWD0 TWCK1 TWD1 URXD UTXD RXD0 TXD0 SCK0 ...
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Figure 2-3. SAM3X4/8E (144 pins) Block Diagram System Controller TST PCK0-PCK2 PLLA UPLL XIN OSC XOUT WDT RC 12/8/4 M SHDN FWUP XIN32 XOUT32 ERASE NRSTB VDDBU VDDCORE VDDUTMI NRST PIOA PIOC PIOE TWCK0 TWD0 TWCK1 TWD1 URXD UTXD RXD0 ...
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Figure 2-4. SAM3X8H (217 pins) Block Diagram System Controller TST PCK0-PCK2 PLLA UPLL PMC XIN OSC XOUT WDT SM RC 12/8/4 M SHDN SUPC FWUP XIN32 OSC 32K XOUT32 RC 32k ERASE 8 GPBREG NRSTB RTT RTC VDDBU VDDCORE RSTC ...
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Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function VDDIO Peripherals I/O Lines Power Supply VDDUTMI USB UTMI+ Interface Power Supply VDDOUT Voltage Regulator Output Voltage Regulator, ADC and DAC Power VDDIN Supply GNDUTMI USB UTMI+ ...
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Table 3-1. Signal Description List (Continued) Signal Name Function TCK/SWCLK Test Clock/Serial Wire Clock TDI Test Data In Test Data Out / Trace Asynchronous Data TDO/TRACESWO Out Test Mode Select /Serial Wire TMS/SWDIO Input/Output JTAGSEL JTAG Selection Flash and NVM ...
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Table 3-1. Signal Description List (Continued) Signal Name Function PA0 - PA31 Parallel IO Controller A PB0 - PB31 Parallel IO Controller B PC0 - PC30 Parallel IO Controller C PD0 - PD30 Parallel IO Controller D PE0 - PE31 ...
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Table 3-1. Signal Description List (Continued) Signal Name Function NANDOE NAND Flash Output Enable NANDWE NAND Flash Write Enable NANDRDY NAND Ready NANDCLE NAND Flash Command Line Enable NANDALE NAND Flash Address Line Enable SDCK SDRAM Clock SDCKE SDRAM Clock ...
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Table 3-1. Signal Description List (Continued) Signal Name Function ECRSDV Carrier Sense and Data Valid ERX0 - ERX3 Receive Data ERXER Receive Error ECRS Carrier Sense ECOL Collision Detected EMDC Management Data Clock EMDIO Management Data Input/Output CANRXx CAN Input ...
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Table 3-1. Signal Description List (Continued) Signal Name Function TWCKx TWIx Two-wire Serial Clock AD0 - AD14 Analog Inputs ADTRG ADC Trigger ADVREF ADC and DAC Reference DAC0 DAC channel 0 analog output DAC1 DAC channel 1 analog output DATRG ...
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Design Considerations In order to facilitate schematic capture when using a SAM3X/A design, Atmel provides a “Sche- matics Checklist” Application Note. See SAM3X/A 14 http://www.atmel.com/products/AT91/ 11057A–ATARM–17-Feb-12 ...
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Package and Pinout 4.1 SAM3A4/8C and SAM3X4/8C Package and Pinout The SAM3A4/8C and SAM3X4/8C are available in 100-lead LQFP and 100-ball LFBGA packages. 4.1.1 100-lead LQFP Package Outline Figure 4-1. 4.1.2 100-ball LFBGA Package Outline Figure 4-2. 11057A–ATARM–17-Feb-12 Orientation ...
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LQFP Pinout Table 4-1. 100-lead LQFP SAM3A4/8C and SAM3X4/8C Pinout 1 PB26 2 PA9 3 PA10 4 PA11 5 PA12 6 PA13 7 PA14 8 PA15 9 PA17 10 VDDCORE 11 VDDIO 12 GND 13 PA0 14 PA1 ...
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LFBGA Pinout Table 4-2. 100-ball LFBGA SAM3X4/8E Package and Pinout A1 PB26 A2 PB24 A3 PB22 A4 PB14 A5 PC0 A6 PB9 A7 PB6 A8 PB2 A9 PA28 A10 PA26 B1 PA11 B2 PB25 B3 PB23 B4 PA10 ...
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SAM3X4/8E Package and Pinout The SAM3X4/8E is available in 144-lead LQFP and 144-ball LFBGA packages. 4.2.1 144-lead LQFP Package Outline Figure 4-3. Orientation of the 144-lead LQFP Package 4.2.2 144-ball LFBGA Package Outline The 144-Ball LFBGA package has a ...
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LQFP Pinout Table 4-3. 144-lead LQFP SAM3X4/8E Pinout 1 PB26 2 PA9 3 PA10 4 PA11 5 PA12 6 PA13 7 PA14 8 PA15 9 PA17 10 VDDCORE 11 VDDIO 12 GND 13 PD0 14 PD1 15 PD2 ...
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LFBGA Pinout Table 4-4. 144-ball LFBGA SAM3X4/8E Pinout A1 PA9 A2 PB23 A3 PB14 A4 PC26 A5 PC24 A6 PC20 A7 PB10 A8 PB6 A9 PB4 A10 PC4 A11 PA28 A12 PA27 B1 PA10 B2 PB26 B3 PB24 ...
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SAM3X8H Package and Pinout The SAM3X8H is available in a 217-ball LFBGA package. 4.3.1 217-ball LFBGA Package Outline The 217-Ball LFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimen- sions are ...
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LFBGA Pinout Table 4-5. 217-ball LFBGA SAM3X8H Pinout A1 PB26 A2 PE24 A3 PB23 A4 PC28 A5 PC25 A6 PC21 D10 A7 PE18 D11 A8 PE17 D12 A9 PB10 D13 A10 PE15 D14 A11 PE12 D15 A12 PE9 ...
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Table 4-5. 217-ball LFBGA SAM3X8H Pinout (Continued) C4 PB22 C5 PC27 C6 PC24 C7 PC20 C8 PC0 C9 PB11 C10 PE13 C11 PE10 C12 PB8 C13 PB4 C14 PC4 C15 PA29 C16 PA21 C17 PE8 D1 PA15 D2 PA14 D3 ...
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Power Considerations 5.1 Power Supplies The SAM3X/A series product has several types of power supply pins: • VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage ranges from 1.62V to 1.95V. • VDDIO pins: Power the ...
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Typical Powering Schematics The SAM3X/A series supports a 1.62V-3.6V single supply mode. The internal regulator input connected to the source and its output feeds VDDCORE. schematics. Figure 5-1. Note: 11057A–ATARM–17-Feb-12 Single Supply Main Supply (1.8V-3.6V) Restrictions For USB, VDDUTMI ...
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Figure 5-2. Note: SAM3X/A 26 Core Externally Supplied Main Supply (1.62V-3.6V) VDDCORE Supply (1.62V-1.95V) Restrictions For USB, VDDUTMI needs to be greater than 3.0V. For ADC, VDDANA needs to be greater than 2.0V. For DAC, VDDANA needs to be greater ...
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Figure 5-3. Note: 5.4 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The power management controller can be used to adapt the ...
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The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz Oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are off. Backup Mode is based on ...
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The processor can be awakened from an interrupt if WFI instruction of the Cortex M3 is used, or from an event if the WFE instruction is used to enter this mode. 5.5.4 Low Power Mode Summary Table The modes detailed ...
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Wake-up Sources The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply. Figure 5-4. Wake-up Source SMEN sm_int RTCEN ...
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Fast Start-Up The SAM3X/A series allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up ...
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Input/Output Lines The SAM3X/A has different kinds of input/output (I/O) lines, such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functions thanks to multiplexing capabilities of the PIO controllers. The same PIO line can be ...
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Table 6-1. System I/O Configuration Pin List SYSTEM_IO Default Function Bit Number Peripheral TDO/TRACESWO A Note: 6.2.1 Serial Wire JTAG Debug Port (SWJ-DP) Pins The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided ...
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NRST Pin The NRST pin is bidirectional handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components, or asserted low externally to reset the microcontroller. It will ...
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Product Mapping Figure 7-1. SAM3X/A Product Mapping Code Boot Memory Internal Flash 0 Internal Flash 1 Internal ROM Reserved HALF_FLASHSIZE address: - 512kB products: 0x000C0000 - 256kB products: 0x000A0000 - 128kB products: 0x00090000 SRAM SRAM0 SRAM1 NFC (SRAM) UOTGHS ...
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Memories 8.1 Embedded Memories 8.1.1 Internal SRAM • The 144-pin and 217-pin SAM3X8 product embeds a total of 100 Kbytes high-speed SRAM (64 Kbytes SRAM0, 32 Kbytes SRAM1 and 4 Kbytes NAND Flash Controller). • The 100-pin SAM3A/X8 product ...
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The user can choose between high performance or lower current consumption by selecting either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the ...
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The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when TST, PA0, PA1 are set to high, PA2 and PA3 ...
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The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0. 8.1.3.10 GPNVM Bits The SAM3X/A series features three GPNVM bits that can be cleared or set respectively through ...
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Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time • Slow Clock mode supported 8.2.3 NAND Flash ...
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SDR-SDRAM Controller (217-pin SAM3X only) • Numerous configurations supported – 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16-bit Data Path • Programming facilities – Word, half-word, byte access ...
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System Controller The System Controller is a set of peripherals, which allow handling of key elements of the sys- tem such as power, resets, clocks, time, interrupts, watchdog, etc... The System Controller User Interface also embeds the registers allowing ...
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Figure 9-1. System Controller Block Diagram VDDBU FWUP SHDN NRSTB Zero-Power Power-on Reset General Purpose Backup Registers SLCK RTC SLCK RTT osc32k_xtal_en XIN32 Xtal 32 kHz Oscillator XOUT32 Embedded 32 kHz RC osc32k_rc_en Oscillator Backup Power Supply vddcore_nreset NRST FSTT0 ...
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System Controller and Peripherals Mapping Please refer to All the peripherals are in the bit band region and are mapped in the bit band alias region. 9.2 Power-on-Reset, Brownout and Supply Monitor The SAM3X/A embeds three features to monitor, ...
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Peripherals 10.1 Peripheral Identifiers Table 10-1 required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Note that some Peripherals are always ...
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Table 10-1. Peripheral Identifiers (Continued) Instance ID Instance Name 29 TC2 30 TC3 31 TC4 32 TC5 33 TC6 34 TC7 35 TC8 36 PWM 37 ADC 38 DACC 39 DMAC 40 UOTGHS 41 TRNG 42 EMAC 43 CAN0 44 ...
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Note that some peripheral function, which are output only, might be duplicated within both tables. 10.3.1 PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A PA0 CANTX0 PA1 CANRX0 PA2 TIOA1 PA3 TIOB1 ...
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PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B (PIOB) I/O Line Peripheral A (1) PB0 ETXCK/EREFCK (1) PB1 ETXEN (1) PB2 ETX0 (1) PB3 ETX1 (1) PB4 ECRSDV/ERXDV (1) PB5 ERX0 (1) PB6 ERX1 (1) PB7 ...
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PIO Controller C Multiplexing Table 10-4. Multiplexing on PIO Controller C (PIOC) I/O Line Peripheral A PC0 PC1 PC2 D0 PC3 D1 PC4 D2 PC5 D3 PC6 D4 PC7 D5 PC8 D6 PC9 D7 PC10 D8 PC11 D9 PC12 ...
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PIO Controller D Multiplexing Table 10-5. Multiplexing on PIO Controller D (PIOD) I/O Line Peripheral A PD0 A10 PD1 A11 PD2 A12 PD3 A13 PD4 A14 PD5 A15 PD6 A16/BA0 PD7 A17/BA1 PD8 A21/NANDALE PD9 A22/NANDCLE PD10 NWR1/NBS1 PD11 ...
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PIO Controller E Multiplexing Table 10-6. Multiplexing on PIO Controller E (PIOE) I/O Line Peripheral A PE0 A19 PE1 A20 PE2 A21/NANDALE PE3 A22/NANDCLE PE4 A23 PE5 NCS4 PE6 NCS5 PE7 PE8 PE9 TIOA3 PE10 TIOB3 PE11 TIOA4 PE12 ...
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PIO Controller F Multiplexing Table 10-7. Multiplexing on PIO Controller F (PIOF) I/O Line Peripheral A PF0 SPI1_NPCS1 PF1 SPI1_NPCS2 PF2 SPI1_NPCS3 PF3 PWMH3 PF4 CTS3 PF5 RTS3 SAM3X/A 52 Peripheral B Extra Function Comments 217 pins 217 pins ...
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ARM Cortex M3 Processor 11.1 About this section This section provides the information required for application and system-level software devel- opment. It does not provide information on debug components, features, or operation. This material is for microcontroller software ...
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Figure 11-1. Typical Cortex-M3 implementation The Cortex-M3 processor is built on a high-performance processor core, with ...
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System level interface The Cortex-M3 processor provides multiple interfaces using AMBA speed, low latency memory accesses. It supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe Boolean data handling. The ...
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System timer The system timer, SysTick 24-bit count-down timer. Use this as a Real Time Operating Sys- tem (RTOS) tick timer simple counter. 11.3.4.4 Memory protection unit The Memory protection unit (MPU) improves system ...
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The proces- sor implements two stacks, the main stack and the process stack, with independent copies of the stack pointer, see In Thread mode, the CONTROL ...
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Table 11-2. Name R0-R12 MSP PSP LR PC PSR ASPR IPSR EPSR PRIMASK FAULTMASK BASEPRI CONTROL 1. 2. 11.4.3.1 General-purpose registers R0-R12 are 32-bit general-purpose registers for data operations. 11.4.3.2 Stack Pointer The Stack Pointer (SP) is register R13. In ...
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Program Counter The Program Counter (PC) is register R15. It contains the current program address. Bit[0] is always 0 because instruction fetches must be halfword aligned. On reset, the processor loads the PC with the value of the reset ...
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The PSR bit assignments are Access these registers individually combination of any two or all three registers, using the register name as an argument to the MSR ...
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C Carry or borrow flag add operation did not result in a carry bit or subtract operation resulted in a borrow bit 1 = add operation resulted in a carry bit or subtract operation did not result ...
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Execution Program Status Register The EPSR contains the Thumb state bit, and the execution state bits for either the: • If-Then (IT) instruction • Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple ...
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Priority Mask Register The PRIMASK register prevents activation of all exceptions with configurable priority. See the register summary • PRIMASK 0: no effect 1: prevents the activation of all exceptions ...
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Base Priority Mask Register The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with same or lower priority level as the BASEPRI value. ...
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CONTROL register The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. See the register summary in its attributes. The bit assignments are ...
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Exceptions and interrupts The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses handler mode ...
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The following sections give more information about the CMSIS: • “Power management programming hints” on page 86 • “Intrinsic functions” on page 90 • “The CMSIS mapping of the Cortex-M3 NVIC registers” on page 153 • “NVIC programming hints” on ...
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Memory regions, types and attributes The memory map and the programming of the MPU split the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes ...
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However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered memory. For two memory access instructions A1 and A2 occurs before A2 in program order, the ordering of the memory accesses caused by two ...
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Additional memory access constraints for shared memory When a system includes shared memory, some memory regions have additional access con- straints, and some regions are subdivided, as Table 11-5. Address range 0x00000000- 0x1FFFFFFF 0x20000000- 0x3FFFFFFF 0x40000000- 0x5FFFFFFF 0x60000000- 0x7FFFFFFF ...
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DSB The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transac- tions complete before subsequent instructions execute. See 11.5.4.3 ISB The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is recognizable by subsequent ...
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Table 11-6. Address range 0x20000000- 0x200FFFFF 0x22000000- 0x23FFFFFF Table 11-7. Address range 0x40000000- 0x400FFFFF 0x42000000- 0x43FFFFFF A word access to the SRAM ...
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Figure 11-2. Bit-band mapping 0x23FFFFFC 0x2200001C 7 7 11.5.5.1 Directly accessing an alias region Writing to a word in the alias region updates a single bit in the bit-band region. Bit[0] of the value written to a word in the ...
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Little-endian format In little-endian format, the processor stores the least significant byte of a word at the lowest- numbered byte, and the most significant byte at the highest-numbered byte. For example: Address A A+1 A+2 A+3 11.5.7 Synchronization primitives ...
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No write was performed. This indicates that the value returned the first step might be out of date. The software must retry the read-modify-write sequence, Software can use the synchronization primitives to implement a semaphores as follows: • Use ...
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Exception model This section describes the exception model. 11.6.1 Exception states Each exception is in one of the following states: 11.6.1.1 Inactive The exception is not active and not pending. 11.6.1.2 Pending The exception is waiting to be serviced ...
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Memory management fault A memory management fault is an exception that occurs because of a memory protection related fault. The MPU or the fixed memory protection constraints determines this fault, for both instruction and data memory transactions. This fault ...
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Table 11-9. Properties of the different exception types (Continued) IRQ ( Exception number Exception (1) 1) number type Memory 4 -12 management fault 5 -11 Bus fault 6 -10 Usage fault 7- SVCall 12- ...
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System handlers NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions that are han- dled by system handlers. 11.6.4 Vector table The vector table contains the reset value of the stack pointer, and the start addresses, ...
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Exception priorities As Table 11-9 on page 77 • a lower priority value indicating a higher priority • configurable priorities for all exceptions except Reset, Hard fault. If software does not configure any priorities, then all exceptions with a ...
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When one exception preempts another, the exceptions are called nested exceptions. See “Exception entry” on page 81 11.6.7.2 Return This occurs when the exception handler is completed, and: • there is no pending exception with sufficient priority to be serviced ...
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The stack frame includes the return address. This is the address of the next instruction in the interrupted program. This value is restored to the PC at exception return so that the interrupted program resumes. In parallel to the stacking ...
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Fault handling Faults are a subset of the exceptions, see ate a fault: – a bus error on: – an instruction fetch or vector table load – a data access • an internally-detected error such as an undefined instruction ...
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Fault escalation and hard faults All faults exceptions except for hard fault have configurable exception priority, see dler Priority Registers” on page faults, see Usually, the exception priority, together with the values of the exception mask registers, deter- mines ...
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Lockup The processor enters a lockup state if a hard fault occurs when executing the hard fault han- dlers. When the processor is in lockup state it does not execute any instructions. The processor remains in lockup state until: ...
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Wakeup from WFI or sleep-on-exit Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception entry. Some embedded systems might have to execute system restore tasks after the processor wakes up, and ...
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Table 11-13. Cortex-M3 instructions (Continued) Mnemonic B BFC BFI BIC, BICS BKPT BL BLX BX CBNZ CBZ CLREX CLZ CMN, CMNS CMP, CMPS CPSID CPSIE DMB DSB EOR, EORS ISB IT LDM LDMDB, LDMEA LDMFD, LDMIA LDR LDRB, LDRBT LDRD ...
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Table 11-13. Cortex-M3 instructions (Continued) Mnemonic LDRSB, LDRSBT LDRSH, LDRSHT LDRT LSL, LSLS LSR, LSRS MLA MLS MOV, MOVS MOVT MOVW, MOV MRS MSR MUL, MULS MVN, MVNS NOP ORN, ORNS ORR, ORRS POP PUSH RBIT REV REV16 REVSH ROR, ...
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Table 11-13. Cortex-M3 instructions (Continued) Mnemonic SSAT STM STMDB, STMEA STMFD, STMIA STR STRB, STRBT STRD STREX STREXB STREXH STRH, STRHT STRT SUB, SUBS SUB, SUBW SVC SXTB SXTH TBB TBH TEQ TST UBFX UDIV UMLAL UMULL USAT UXTB UXTH ...
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Intrinsic functions ANSI cannot directly access some Cortex-M3 instructions. This section describes intrinsic func- tions that can generate these instructions, provided by the CMIS and that might be provided compiler compiler does not ...
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Table 11-15. CMSIS intrinsic functions to access the special registers (Continued) Special register MSP PSP 11.11 About the instruction descriptions The following sections give more information about using the instructions: • “Operands” on page 91 • “Restrictions when using PC ...
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Constant You specify an Operand2 constant in the form: #constant where constant can be: • any constant that can be produced by shifting an 8-bit value left by any number of bits within a 32-bit word • any constant ...
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Shift Operations Register shift operations move the bits in a register left or right by a specified number of bits, the shift length. Register shift can be performed: • directly by the instructions ASR, LSR, LSL, ROR, and RRX, ...
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more and the carry flag is updated updated to 0. Figure 11-5. LSR # 11.11.4.3 LSL Logical shift left by n bits moves the right-hand 32-n bits of the register ...
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Figure 11-7. ROR #3 31 11.11.4.5 RRX Rotate right with extend moves the bits of the register Rm to the right by one bit. And it copies the carry flag into bit[31] of the result. See When the instruction is ...
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If the offset is too big, the assembler produces an error. • For B, BL, CBNZ, and CBZ instructions, the value of the PC ...
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V For more information about the APSR see A carry occurs: • if the result of an addition is greater than or equal to 2 • if the result of a subtraction is positive or zero • as the result ...
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Absolute value The example below shows the use of a conditional instruction to find the absolute value of a number ABS(R1). MOVS R0 RSBMI R0, R1, #0 11.11.7.4 Compare and update value The example ...
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Memory access instructions Table 11-17 Table 11-17. Memory access instructions Mnemonic ADR CLREX LDM{mode} LDR{type} LDR{type} LDR{type}T LDR LDREX{type} POP PUSH STM{mode} STR{type} STR{type} STR{type}T STREX{type} 11.12.1 ADR Load PC-relative address. 11.12.1.1 Syntax ADR{cond} Rd, label where: cond Rd ...
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Values of label must be within the range of 4095 to +4095 from the address in the PC. You might have to use the .W suffix to get the maximum offset range or to generate addresses that are not word-aligned. ...
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Operation LDR instructions load one or two registers with a value from memory. STR instructions store one or two register values to memory. Load and store instructions with immediate offset can use the following addressing modes: 11.12.2.3 Offset addressing ...
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Rt can be SP for word stores only • Rt must not be PC • Rn must not be PC • Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms. 11.12.2.7 Condition flags These ...
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Operation LDR instructions load a register with a value from memory. STR instructions store a register value into memory. The memory address to load from or store offset from the register Rn. The offset is ...
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SH - cond Rt Rn offset 11.12.4.2 Operation These load and store instructions perform the same function as the memory access instructions with immediate offset, see these instructions have only unprivileged access even when used in privileged software. When used ...
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Rt Rt2 label 11.12.5.2 Operation LDR loads a register with a value from a PC-relative memory address. The memory address is specified by a label offset from the PC. The value to load or store can be ...
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LDM and STM Load and Store Multiple registers. 11.12.6.1 Syntax op{addr_mode}{cond} Rn{!}, reglist where: op LDM STM addr_mode IA DB cond present the final address, that is loaded from or stored to, is written ...
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The accesses happen in order of decreasing register numbers, with the highest numbered regis- ter using the highest memory address and the lowest number register using the lowest memory address. If the writeback suffix is specified, the value of Rn ...
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Operation PUSH stores registers on the stack in order of decreasing the register numbers, with the highest numbered register using the highest memory address and the lowest numbered register using the lowest memory address. POP loads registers from the ...
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Operation LDREX, LDREXB, and LDREXH load a word, byte, and halfword respectively from a memory address. STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a memory address. The address used in any Store-Exclusive ...
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CLREX Clear Exclusive. 11.12.9.1 Syntax CLREX{cond} where: cond 11.12.9.2 Operation Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination register and fail to perform the store useful in exception handler ...
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General data processing instructions Table 11-20 Table 11-20. Data processing instructions Mnemonic Brief description ADC Add with Carry ADD Add ADDW Add AND Logical AND ASR Arithmetic Shift Right BIC Bit Clear CLZ Count leading zeros CMN Compare Negative ...
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ADD, ADC, SUB, SBC, and RSB Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract. 11.13.1.1 Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 where: op ADD ADC SUB SBC RSB S result of the operation, ...
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Rd can be SP only in ADD and SUB, and only with the additional restrictions: – Rn must also be SP – any shift in Operand2 must be limited to a maximum of 3 bits using LSL • Rn ...
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Multiword arithmetic examples 11.13.1.7 64-bit addition The example below shows two instructions that add a 64-bit integer contained in R2 and R3 to another 64-bit integer con- tained in R0 and R1, and place the result in R4 and ...
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Restrictions Do not use SP and do not use PC. 11.13.2.4 Condition flags specified, these instructions: • update the N and Z flags according to the result • can update the C flag during the calculation ...
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ASR, LSL, LSR, ROR, and RRX Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend. 11.13.3.1 Syntax op{S}{cond} Rd, Rm, Rs op{S}{cond} Rd, Rm, #n RRX{S}{cond} Rd, Rm where: op ASR LSL ...
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C flag is updated to the last bit shifted out, except when the shift length is 0, see Operations” on page 11.13.3.5 Examples ASR R7, R8 Arithmetic shift right by 9 bits LSLS R1, R2, #3 ...
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CMP and CMN Compare and Compare Negative. 11.13.5.1 Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where: cond Rn Operand2 details of the options. 11.13.5.2 Operation These instructions compare the value in a register with Operand2. They update the condition ...
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MOV and MVN Move and Move NOT. 11.13.6.1 Syntax MOV{S}{cond} Rd, Operand2 MOV{cond} Rd, #imm16 MVN{S}{cond} Rd, Operand2 where: S result of the operation, see cond Rd Operand2 details of the options. imm16 11.13.6.2 Operation The MOV instruction copies ...
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PC is ignored • a branch occurs to the address created by forcing bit[0] of that value to 0. Though it is possible to use MOV as a branch instruction, ARM strongly ...
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MOVT Move Top. 11.13.7.1 Syntax MOVT{cond} Rd, #imm16 where: cond Rd imm16 11.13.7.2 Operation MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. The write does not affect Rd[15:0]. The MOV, MOVT ...
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REV, REV16, REVSH, and RBIT Reverse bytes and Reverse bits. 11.13.8.1 Syntax op{cond} Rd, Rn where: op REV REV16 Reverse byte order in each halfword independently. REVSH Reverse byte order in the bottom halfword, and sign extend to 32 ...
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TST and TEQ Test bits and Test Equivalence. 11.13.9.1 Syntax TST{cond} Rn, Operand2 TEQ{cond} Rn, Operand2 where: cond Rn Operand2 details of the options. 11.13.9.2 Operation These instructions test the value in a register against Operand2. They update the ...
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Multiply and divide instructions Table 11-21 Table 11-21. Multiply and divide instructions Mnemonic MLA MLS MUL SDIV SMLAL SMULL UDIV UMLAL UMULL SAM3X/A SAM3X/A 124 124 shows the multiply and divide instructions: Brief description Multiply with Accumulate, 32-bit result ...
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MUL, MLA, and MLS Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and pro- ducing a 32-bit result. 11.14.1.1 Syntax MUL{S}{cond} {Rd,} Rn Multiply MLA{cond} Rd, Rn, Rm, Ra MLS{cond} Rd, Rn, Rm, Ra ...
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UMULL, UMLAL, SMULL, and SMLAL Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and pro- ducing a 64-bit result. 11.14.2.1 Syntax op{cond} RdLo, RdHi, Rn, Rm where: op UMULL Unsigned Long Multiply. UMLAL Unsigned Long Multiply, ...
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SDIV and UDIV Signed Divide and Unsigned Divide. 11.14.3.1 Syntax SDIV{cond} {Rd,} Rn, Rm UDIV{cond} {Rd,} Rn, Rm where: cond 11.14.3.2 Operation SDIV performs a signed integer division of the value the value ...
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Saturating instructions This section describes the saturating instructions, SSAT and USAT. 11.15.1 SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating. 11.15.1.1 Syntax op{cond} Rd, # shift #s} where: ...
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Restrictions Do not use SP and do not use PC 11.15.1.4 Condition flags These instructions do not affect the condition code flags. If saturation occurs, these instructions set the Q flag to 1. 11.15.1.5 Examples SSAT R7, #16, R7, ...
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Bitfield instructions Table 11-22 Table 11-22. Packing and unpacking instructions Mnemonic BFC BFI SBFX SXTB SXTH UBFX UXTB UXTH SAM3X/A SAM3X/A 130 130 shows the instructions that operate on adjacent sets of bits in registers or bitfields: Brief description ...
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BFC and BFI Bit Field Clear and Bit Field Insert. 11.16.1.1 Syntax BFC{cond} Rd, #lsb, #width BFI{cond} Rd, Rn, #lsb, #width where: cond Rd Rn lsb width 11.16.1.2 Operation BFC clears a bitfield in a register. It clears width ...
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SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract. 11.16.2.1 Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width where: cond Rd Rn lsb width 11.16.2.2 Operation SBFX extracts a bitfield from one register, ...
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SXT and UXT Sign extend and Zero extend. 11.16.3.1 Syntax SXTextend{cond} {Rd ROR #n} UXTextend{cond} {Rd ROR #n} where: extend B H cond Rd Rm ROR #n ROR #8 Value from Rm is rotated right ...
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Branch and control instructions Table 11-23 Table 11-23. Branch and control instructions Mnemonic B BL BLX BX CBNZ CBZ IT TBB TBH SAM3X/A SAM3X/A 134 134 shows the branch and control instructions: Brief description Branch Branch with Link Branch ...
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B, BL, BX, and BLX Branch instructions. 11.17.1.1 Syntax B{cond} label BL{cond} label BX{cond} Rm BLX{cond} Rm where BLX cond label but the address to branch to is created by changing bit[0] to ...
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PC in the BLX instruction • for BX and BLX, bit[ must be 1 for correct execution but a branch occurs to the target address created by changing bit[ • when any ...
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CBZ and CBNZ Compare and Branch on Zero, Compare and Branch on Non-Zero. 11.17.2.1 Syntax CBZ Rn, label CBNZ Rn, label where: Rn label 11.17.2.2 Operation Use the CBZ or CBNZ instructions to avoid changing the condition code flags ...
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IT If-Then condition instruction. 11.17.3.1 Syntax IT{x{y{z}}} cond where cond The condition switch for the second, third and fourth instruction in the IT block can be either possible to use AL (the ...
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PC must either be outside an IT block or must be the last instruction inside the IT block. These are: – ADD PC, PC, Rm – MOV PC, Rm – B, ...
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TBB and TBH Table Branch Byte and Table Branch Halfword. 11.17.4.1 Syntax TBB [Rn, Rm] TBH [Rn, Rm, LSL #1] where: Rn then the address of the table is the address of the byte immediately following the TBB or ...
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Examples ADR.W R0, BranchTable_Byte TBB [R0, R1] Case1 ; an instruction sequence follows Case2 ; an instruction sequence follows Case3 ; an instruction sequence follows BranchTable_Byte DCB 0 DCB ((Case2-Case1)/2) DCB ((Case3-Case1)/2) TBH [PC, R1, LSL #1] BranchTable_H DCI ...
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Miscellaneous instructions Table 11-25 Table 11-25. Miscellaneous instructions Mnemonic BKPT CPSID CPSIE DMB DSB ISB MRS MSR NOP SEV SVC WFE WFI SAM3X/A SAM3X/A 142 142 shows the remaining Cortex-M3 instructions: Brief description Breakpoint Change Processor State, Disable Interrupts ...
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BKPT Breakpoint. 11.18.1.1 Syntax BKPT #imm where: imm 11.18.1.2 Operation The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. imm ...
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CPS Change Processor State. 11.18.2.1 Syntax CPSeffect iflags where: effect IE ID iflags i f 11.18.2.2 Operation CPS changes the PRIMASK and FAULTMASK special register values. See registers” on page 62 11.18.2.3 Restrictions The restrictions are: • use CPS ...
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DMB Data Memory Barrier. 11.18.3.1 Syntax DMB{cond} where: cond 11.18.3.2 Operation DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit ...
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ISB Instruction Synchronization Barrier. 11.18.5.1 Syntax ISB{cond} where: cond 11.18.5.2 Operation ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from memory again, after the ...
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MRS Move the contents of a special register to a general-purpose register. 11.18.6.1 Syntax MRS{cond} Rd, spec_reg where: cond Rd spec_reg PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. 11.18.6.2 Operation Use MRS in combination with MSR as part of a ...
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MSR Move the contents of a general-purpose register into the specified special register. 11.18.7.1 Syntax MSR{cond} spec_reg, Rn where: cond Rn spec_reg PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. 11.18.7.2 Operation The register access operation in MSR depends on the ...
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NOP No Operation. 11.18.8.1 Syntax NOP{cond} where: cond 11.18.8.2 Operation NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage. Use NOP for padding, for ...
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SVC Supervisor Call. 11.18.10.1 Syntax SVC{cond} #imm where: cond imm 11.18.10.2 Operation The SVC instruction causes the SVC exception. imm is ignored by the processor. If required, it can be retrieved by the exception handler to determine what service ...
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WFI Wait for Interrupt. 11.18.12.1 Syntax WFI{cond} where: cond 11.18.12.2 Operation WFI is a hint instruction that suspends execution until one of the following events occurs: • an exception • a Debug Entry request, regardless of whether Debug is ...
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About the Cortex-M3 peripherals The address map of the Private peripheral bus (PPB) is: Table 11-26. Core peripheral register regions Address 0xE000E008- 0xE000E00F 0xE000E010- 0xE000E01F 0xE000E100- 0xE000E4EF 0xE000ED00- 0xE000ED3F 0xE000ED90- 0xE000EDB8 0xE000EF00- 0xE000EF03 In register descriptions: • the register ...
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Nested Vectored Interrupt Controller This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: • interrupts. • A programmable priority level of 0-15 for each interrupt. A higher level ...
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Interrupt Priority Registers map to an array of 4-bit integers, so that the array IP[0] to IP[29] corresponds to the registers IPR0-IPR7, and the array entry IP[n] holds the interrupt priority for interrupt n. ...
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Interrupt Set-enable Registers The ISER0-ISER1 register enables interrupts, and show which interrupts are enabled. See: • the register summary in • Table 11-28 on page 154 The bit assignments are • ...
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Interrupt Clear-enable Registers The ICER0-ICER1 register disables interrupts, and shows which interrupts are enabled. See: • the register summary in • Table 11-28 on page 154 The bit assignments are • ...
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Interrupt Set-pending Registers The ISPR0-ISPR1 register forces interrupts into the pending state, and shows which interrupts are pending. See: • the register summary in • Table 11-28 on page 154 The bit assignments are ...
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Interrupt Clear-pending Registers The ICPR0-ICPR1 register removes the pending state from interrupts, and show which inter- rupts are pending. See: • the register summary in • Table 11-28 on page 154 The bit assignments are ...
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Interrupt Active Bit Registers The IABR0-IABR1 register indicates which interrupts are active. See: • the register summary in • Table 11-28 on page 154 The bit assignments are • ACTIVE Interrupt ...
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Interrupt Priority Registers The IPR0-IPR7 registers provide a 4-bit priority field for each interrupt (See the “Peripheral Iden- tifiers” section of the datasheet for more details). These registers are byte-accessible. See the register summary in fields, that map up ...
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IPR2 11.20.7.5 IPR1 11.20.7.6 IPR0 • Priority, byte offset 3 • Priority, byte offset 2 ...
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Find the IPR number and byte offset for interrupt N as follows: • the corresponding IPR number given DIV 4 • the byte offset of the required Priority field in this register is N ...
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Level-sensitive interrupts The processor supports level-sensitive interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typ- ically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. When the ...
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NVIC design hints and tips Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. See the individual register descriptions for the supported access sizes. A interrupt can enter pending state even ...
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System control block The System control block (SCB) provides system implementation information, and system con- trol. This includes configuration, control, and reporting of the system exceptions. The system control block registers are: Table 11-30. Summary of the system control ...
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Auxiliary Control Register The ACTLR provides disable bits for the following processor functions: • IT folding • write buffer use for accesses to the default memory map • interruption of multi-cycle instructions. See the register summary in ments are: ...
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CPUID Base Register The CPUID register contains the processor part number, version, and implementation informa- tion. See the register summary in are Variant PartNo • Implementer Implementer code: 0x41 = ARM ...
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Interrupt Control and State Register The ICSR: • provides: – set-pending and clear-pending bits for the PendSV and SysTick exceptions • indicates: – the exception number of the exception being processed – whether there are preempted active exceptions – ...
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PENDSTSET RW SysTick exception set-pending bit. Write effect 1: changes SysTick exception state to pending. Read: 0: SysTick exception is not pending 1: SysTick exception is pending. • PENDSTCLR WO SysTick exception clear-pending bit. Write ...
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RETTOBASE RO Indicates whether there are preempted active exceptions: 0: there are preempted active exceptions to execute 1: there are no active exceptions, or the currently-executing exception is the only active exception. • VECTACTIVE RO Contains the active exception ...
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Vector Table Offset Register The VTOR indicates the offset of the vector table base address from memory address 0x00000000. See the register summary in The bit assignments are Reserved TBLOFF • ...
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Application Interrupt and Reset Control Register The AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. See the register summary in 165 and To write to this register, ...
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VECTCLRACTIVE WO Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. • VECTRESET WO Reserved for Debug use. This bit reads as 0. ...
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System Control Register The SCR controls features of entry to and exit from low power state. See the register summary in Table 11-30 on page 165 Reserved • SEVONPEND Send Event ...
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Configuration and Control Register The CCR controls entry to Thread mode and enables: • the handlers for hard fault and faults escalated by FAULTMASK to ignore bus faults • trapping of divide by zero and unaligned accesses • access ...
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UNALIGN_TRP Enables unaligned access traps not trap unaligned halfword and word accesses 1: trap unaligned halfword and word accesses. If this bit is set unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, ...
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System Handler Priority Register 1 The bit assignments are • PRI_7 Reserved • PRI_6 Priority of system handler 6, usage fault • PRI_5 Priority of system handler 5, bus fault • ...
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System Handler Priority Register 2 The bit assignments are • PRI_11 Priority of system handler 11, SVCall 11.21.9.3 System Handler Priority Register 3 The bit assignments are ...
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System Handler Control and State Register The SHCSR enables the system handlers, and indicates: • the pending status of the bus fault, memory management fault, and SVC exceptions • the active status of the system handlers. See the register ...
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MONITORACT Debug monitor active bit, reads Debug monitor is active • SVCALLACT SVC call active bit, reads SVC call is active • USGFAULTACT Usage fault exception active bit, reads exception ...
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Configurable Fault Status Register The CFSR indicates the cause of a memory management fault, bus fault, or usage fault. See the register summary The following subsections describe the subregisters that ...
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Memory Management Fault Status Register The flags in the MMFSR indicate the cause of memory access faults. The bit assignments are MMARVALID Reserved • MMARVALID Memory Management Fault Address Register (MMAR) valid flag: 0: value in MMAR ...
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Bus Fault Status Register The flags in the BFSR indicate the cause of a bus access fault. The bit assignments are BFRVALID Reserved • BFARVALID Bus Fault Address Register (BFAR) valid flag: 0: value in BFAR is ...
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PRECISERR Precise data bus error precise data bus error 1: a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. When the processor sets ...
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Usage Fault Status Register The UFSR indicates the cause of a usage fault. The bit assignments are Reserved • DIVBYZERO Divide by zero usage fault divide by zero fault, or divide by zero ...
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When this bit is set to 1, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the EPSR. This bit is not set undefined instruction uses the ...
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Hard Fault Status Register The HFSR gives information about events that activate the hard fault handler. See the register summary in This register is read, write to clear. This means that bits in the register read normally, but writing ...
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Memory Management Fault Address Register The MMFAR contains the address of the location that generated a memory management fault. See the register summary • ADDRESS When the MMARVALID bit of ...
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System control block design hints and tips Ensure software uses aligned accesses of the correct size to access the system control block registers: • except for the CFSR and SHPR1-SHPR3, it must use aligned word accesses • for the ...
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System timer, SysTick The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps to) the value in the LOAD register on the next clock edge, then counts down on subsequent ...
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SysTick Control and Status Register The SysTick CTRL register enables the SysTick features. See the register summary page 190 • COUNTFLAG Returns 1 if timer counted to 0 ...
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SysTick Reload Value Register The LOAD register specifies the start value to load into the VAL register. See the register sum- mary • RELOAD Value to load into the VAL ...
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SysTick Current Value Register The VAL register contains the current value of the SysTick counter. See the register summary in Table 11-33 on page 190 • CURRENT Reads return the current ...
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SysTick Calibration Value Register The CALIB register indicates the SysTick calibration properties. See the register summary in Table 11-33 on page 190 31 30 NOREF SKEW • NOREF Reads as zero. • SKEW ...
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Memory protection unit This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and memory attributes of each region. It supports: • independent ...
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Table 11-34. Memory attributes summary (Continued) Memory type Normal Use the MPU registers to define the MPU regions and their attributes. The MPU registers are: Table 11-35. MPU registers summary Address Name Type 0xE000ED90 TYPE RO 0xE000ED94 CTRL RW 0xE000ED98 ...
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MPU Type Register The TYPE register indicates whether the MPU is present, and if so, how many regions it sup- ports. See the register summary in assignments are • IREGION Indicates ...
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MPU Control Register The MPU CTRL register: • enables the MPU • enables the default memory map background region • enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers. See the ...
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Any access by unprivileged software that does not address an enabled memory region causes a memory management fault. XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit. When the ENABLE ...
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MPU Region Number Register The RNR selects which memory region is referenced by the RBAR and RASR registers. See the register summary • REGION Indicates the MPU region referenced by ...