SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 54

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

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SAM3X/A
Figure 11-1. Typical Cortex-M3 implementation
The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor
delivers exceptional power efficiency through an efficient instruction set and extensively opti-
mized design, providing high-end processing hardware including single-cycle 32x32
multiplication and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly-
coupled system components that reduce processor area while significantly improving interrupt
handling and system debug capabilities. The Cortex-M3 processor implements a version of the
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The Cortex-M3 instruction set provides the exceptional performance expected of a modern 32-
bit architecture, with the high code density of 8-bit and 16-bit microcontrollers.
The Cortex-M3 processor closely integrates a configurable nested interrupt controller (NVIC), to
deliver industry-leading interrupt performance. The NVIC provides up to 16 interrupt priority lev-
els. The tight integration of the processor core and NVIC provides fast execution of interrupt
service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the
hardware stacking of registers, and the ability to suspend load-multiple and store-multiple opera-
tions. Interrupt handlers do not require any assembler stubs, removing any code overhead from
the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from
one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep
sleep function that enables the entire device to be rapidly powered down.
• efficient processor core, system and memories
• ultra-low power consumption with integrated sleep modes
• platform security, with integrated memory protection unit (MPU).
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instruction set, ensuring high code density and reduced program memory requirements.
Cortex-M3
Processor
NVIC
Access
Debug
Interface
Port
Code
Flash
Patch
Protection Unit
Bus Matrix
Processor
Memory
Core
Watchpoints
Peripheral Interface
Data
SRAM and
Viewer
Serial
Wire
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12