SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1190

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

This bit is cleared when UOTGHS_HSTPIPIDR.NBUSYBKEC bit is written to one. This will disable the Transmitted IN Data
interrupt (UOTGHS_HSTPIPIMR.NBUSYBKE).
• SHORTPACKETIE: Short Packet Interrupt Enable
If this bit is set for non-control OUT pipes, a short packet transmission is guaranteed upon ending a DMA transfer, thus sig-
n a l i n g
(UOTGHS_HSTDMACONTROL.END_B_EN) bit and the Automatic Switch (UOTGHS_HSTPIPCFG.AUTOSW) bit are
written to one.
This bit is set when UOTGHS_HSTPIPIER.SHORTPACKETIES bit is written to one. This will enable the Transmitted IN
Data IT (UOTGHS_HSTPIPIMR.SHORTPACKETIE).
This bit is cleared when UOTGHS_HSTPIPIDR.SHORTPACKETEC bit is written to one. This will disable the Transmitted
IN Data IT (UOTGHS_HSTPIPIMR.SHORTPACKETE).
• RXSTALLDE: Received STALLed Interrupt Enable
This bit is set when UOTGHS_HSTPIPIER.RXSTALLDES bit is written to one. This will enable the Transmitted IN Data
interrupt (UOTGHS_HSTPIPIMR.RXSTALLDE).
This bit is cleared when UOTGHS_HSTPIPIDR.RXSTALLDEC bit is written to one. This will disable the Transmitted IN
Data interrupt (UOTGHS_HSTPIPIMR.RXSTALLDE).
• CRCERRE: CRC Error Interrupt Enable
This bit is set when UOTGHS_HSTPIPIER.CRCERRES bit is written to one. This will enable the Transmitted IN Data inter-
rupt (UOTGHS_HSTPIPIMR.CRCERRE).
This bit is cleared when UOTGHS_HSTPIPIDR.CRCERREC bit is written to one. This will disable the Transmitted IN Data
interrupt (UOTGHS_HSTPIPIMR.CRCERRE).
• OVERFIE: Overflow Interrupt Enable
This bit is set when UOTGHS_HSTPIPIER.OVERFIES bit is written to one. This will enable the Transmitted IN Data inter-
rupt (UOTGHS_HSTPIPIMR.OVERFIE).
This bit is cleared when UOTGHS_HSTPIPIDR.OVERFIEC bit is written to one. This will disable the Transmitted IN Data
interrupt (UOTGHS_HSTPIPIMR.OVERFIE).
• NAKEDE: NAKed Interrupt Enable
This bit is set when UOTGHS_HSTPIPIER.NAKEDES bit is written to one. This will enable the Transmitted IN Data inter-
rupt (UOTGHS_HSTPIPIMR.NAKEDE).
This bit is cleared when UOTGHS_HSTPIPIDR.NAKEDEC bit is written to one. This will disable the Transmitted IN Data
interrupt (UOTGHS_HSTPIPIMR.NAKEDE).
• PERRE: Pipe Error Interrupt Enable
This bit is set when UOTGHS_HSTPIPIER.PERRES bit is written to one. This will enable the Transmitted IN Data interrupt
(UOTGHS_HSTPIPIMR.PERRE).
This bit is cleared when UOTGHS_HSTPIPIDR.PERREC bit is written to one. This will disable the Transmitted IN Data
interrupt (UOTGHS_HSTPIPIMR.PERRE).
• TXSTPE: Transmitted SETUP Interrupt Enable
This bit is set when UOTGHS_HSTPIPIER.TXSTPES bit is written to one. This will enable the Transmitted IN Data inter-
rupt (UOTGHS_HSTPIPIMR.TXSTPE).
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11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
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