SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 421

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

25.7.4
Name:
Address:
Access:
Reset:
• LPCB: Low-power Configuration Bits
• PASR: Partial Array Self-refresh (only for low-power SDRAM)
PASR parameter is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks
of the SDRAM array are enabled. Disabled banks are not refreshed in self-refresh mode. This parameter must be set
according to the SDRAM device specification.
After initialization, as soon as PASR field is modified and self-refresh mode is activated, the Extended Mode Register is
accessed automatically and PASR bits are updated before entry in self-refresh mode.This feature is not supported when
SDRAMC shares an external bus with another controller.
• TCSR: Temperature Compensated Self-Refresh (only for low-power SDRAM)
TCSR parameter is transmitted to the SDRAM during initialization to set the refresh interval during self-refresh mode
depending on the temperature of the low-power SDRAM. This parameter must be set according to the SDRAM device
specification.
After initialization, as soon as TCSR field is modified and self-refresh mode is activated, the Extended Mode Register is
accessed automatically and TCSR bits are updated before entry in self-refresh mode.This feature is not supported when
SDRAMC shares an external bus with another controller.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Value
31
23
15
00
01
10
11
–
–
–
7
–
SDRAMC Low Power Register
SDRAMC_LPR
0x400E0210
Read-write
0x0
DEEP_POWER_DOWN
SELF_REFRESH
POWER_DOWN
30
22
14
–
–
–
6
DISABLED
Name
PASR
29
21
13
–
–
5
TIMEOUT
Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down
command is issued to the SDRAM device.
The SDRAM Controller issues a Self-refresh command to the SDRAM device, the
SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves
the Self Refresh Mode when accessed and enters it after the access.
The SDRAM Controller issues a Power-down Command to the SDRAM device after
each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-
down Mode when accessed and enters it after the access.
The SDRAM Controller issues a Deep Power-down command to the SDRAM device.
This mode is unique to low-power SDRAM.
28
20
12
–
–
4
27
19
11
–
–
3
–
DS
Description
26
18
10
–
–
2
–
25
17
–
–
9
1
TCSR
SAM3X/A
SAM3X/A
LPCB
24
16
–
–
8
0
421
421