SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 544

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

28.2.5
28.2.6
28.2.7
544
544
SAM3X/A
SAM3X/A
Processor Clock Controller
SysTick Clock
Peripheral Clock Controller
The PMC features a Processor Clock Controller (HCLK) that implements the Processor Sleep
Mode. The Processor Clock can be disabled by executing the WFI (WaitForInterrupt) or the
WFE (WaitForEvent) processor instruction while the LPM bit is at 0 in the PMC Fast Startup
Mode Register (PMC_FSMR).
The Processor Clock HCLK is enabled after a reset and is automatically re-enabled by any
enabled interrupt. The Processor Sleep Mode is achieved by disabling the Processor Clock,
which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the
product.
When Processor Sleep Mode is entered, the current instruction is finished before the clock is
stopped, but this does not prevent data transfers from other masters of the system bus.
The SysTick calibration value is fixed to 10500 which allows the generation of a time base of 1
ms with SysTick clock to the maximum frequency on MCK divided by 8.
The Power Management Controller controls the clocks of each embedded peripheral by means
of the Peripheral Clock Controller. The user can individually enable and disable the Clock on the
peripherals.
The user can also enable and disable these clocks by writing Peripheral Clock Enable 0
(PMC_PCER0), Peripheral Clock Disable 0 (PMC_PCDR0), Peripheral Clock Enable 1
(PMC_PCER1) and Peripheral Clock Disable 1 (PMC_PCDR1) registers. The status of the
peripheral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR0) and
Peripheral Clock Status Register (PMC_PCSR1).
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are
automatically disabled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peripheral
has executed its last programmed operation before disabling the clock. This is to avoid data cor-
ruption or erroneous behavior of the system.
The bit number within the Peripheral Clock Control registers (PMC_PCER0-1, PMC_PCDR0-1,
and PMC_PCSR0-1) is the Peripheral Identifier defined at the product level. The bit number cor-
responds to the interrupt source number assigned to the peripheral.
In order to save power consumption, the clock of CAN0, CAN1 peripherals can be MCK divided
by a division factor of 1, 2, 4.
This is done by setting the PMC_PCR register. It features a command and acts like a mailbox. To
write the division factor, the user needs to write a WRITE command, the peripheral ID and the
chosen division factor. To read the current division factor, the user just needs to write the READ
command and the peripheral ID. Then a read access on PMC_PCR must be performed.
DIV must not be changed while peripheral is in use or when the peripheral clock is enabled.To
change the clock division factor (DIV) of a peripheral, its clock must first be disabled by writing
either EN to 0 for the corresponding PID (DIV must be kept the same if this method is used), or
writing to PMC_PCDR register. Then a second write must be performed into PMC_PCR with the
new value of DIV and a third write must be performed to enable the peripheral clock (either by
using PMC_PCR or PMC_PCER register).
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12