SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 987

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

38.6.1
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
PWM Clock Generator
Figure 38-2. Functional View of the Clock Generator Block Diagram
The PWM master clock (MCK) is divided in the clock generator module to provide different
clocks available for all channels. Each channel can independently select one of the divided
clocks.
The clock generator is divided in three blocks:
Each linear divider can independently divide one of the clocks of the modulo n counter. The
selection of the clock to be divided is made according to the PREA (PREB) field of the PWM
Clock register (PWM_CLK). The resulting clock clkA (clkB) is the clock selected divided by DIVA
(DIVB) field value.
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) are set to 0. This implies
that after reset clkA (clkB) are turned off.
– a modulo n counter which provides 11 clocks: F
– two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and
F
clkB
MCK
/16, F
MCK
/32, F
MCK
MCK
/64, F
modulo n counter
MCK
/128, F
MCK
PREA
PREB
PWM_MR
/256, F
PWM_MR
Divider A
Divider B
MCK
DIVA
DIVB
MCK
, F
MCK
MCK/2
MCK/4
MCK/8
MCK/16
MCK/32
MCK/64
MCK/128
MCK/256
MCK/512
MCK/1024
MCK
/512, F
/2, F
clkA
clkB
MCK
MCK
/1024
/4, F
MCK
SAM3X/A
SAM3X/A
/8,
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