SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 1061

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

38.7.41
Name:
Address:
Access:
This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in
page
This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the
waveform period.
Only the first 16 bits (channel counter size) are significant.
• CPRDUPD: Channel Period Update
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can
be calculated:
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
1051.
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
31
23
15
–
7
------------------------------------------------------- -
64, 128, 256, 512, or 1024). The resulting period formula will be:
respectively:
64, 128, 256, 512, or 1024). The resulting period formula will be:
---------------------------------------------
2
X
-------------------------------------------------------- -
CRPDUPD
PWM Channel Period Update Register
X
CPRDUPD
MCK
PWM_CPRDUPDx [x=0..7]
0x40094210 [0], 0x40094230 [1], 0x40094250 [2], 0x40094270 [3], 0x40094290 [4], 0x400942B0 [5],
0x400942D0 [6], 0x400942F0 [7]
Write-only
MCK
CPRDUPD
MCK
30
22
14
DIVA
–
6
or
-------------------------------------------------------- -
CRPDUPD
29
21
13
–
5
MCK
DIVB
28
20
12
–
4
CPRDUPD
CPRDUPD
CPRDUPD
27
19
11
–
3
“PWM Write Protect Status Register” on
26
18
10
–
2
25
17
–
9
1
SAM3X/A
SAM3X/A
24
16
–
8
0
1061
1061