SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 155

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

11.20.2
• SETENA
Interrupt set-enable bits.
Write:
0: no effect
1: enable interrupt.
Read:
0: interrupt disabled
1: interrupt enabled.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, assert-
ing its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its
priority.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
31
23
15
7
Interrupt Set-enable Registers
30
22
14
6
The ISER0-ISER1 register enables interrupts, and show which interrupts are enabled. See:
The bit assignments are:
• the register summary in
•
Table 11-28 on page 154
29
21
13
5
28
20
12
4
Table 11-27 on page 153
SETENA bits
SETENA bits
SETENA bits
SETENA bits
for which interrupts are controlled by each register.
27
19
11
3
for the register attributes
26
18
10
2
25
17
9
1
SAM3X/A
SAM3X/A
24
16
8
0
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