SAM3X8E Atmel Corporation, SAM3X8E Datasheet - Page 446

• Manufacturer Part Number: SAM3X8E
• Manufacturer: Atmel Corporation

26.12 Automatic Wait States
26.12.1
Figure 26-13. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2
446
446
SAM3X/A
SAM3X/A
Chip Select Wait States
NBS0, NBS1,
A[23:2]
D[15:0]
A0,A1
NCS0
NCS2
NWE
MCK
NRD
One bit is dedicated to enable/disable NAND Flash scrambling and one bit is dedicated
enable/disable scrambling the off chip SRAM. When at least one external SRAM is scrambled,
the SMSC field must be set in the SMC_OCMS register.
When multiple chip selects (external SRAM) are handled, it is possible to configure the scram-
bling function per chip select using the OCMS field in the SMC_TIMINGS registers.
To scramble the NAND Flash contents, the SRSE field must be set in the SMC_OCMS register.
When NAND Flash memory content is scrambled, the on-chip SRAM page buffer associated for
the transfer is also scrambled.
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to
avoid bus contention or operation conflict.
The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle
cycle ensures that there is no bus contention between the de-activation of one device and the
activation of the next one.
During chip select wait state, all control lines are turned inactive: NBS0 to NBS1, NWR0 to
NWR1, NCS[0..7], NRD lines are all set to 1.
Figure 26-13
Select 2.
NRD_CYCLE
illustrates a chip select wait state between access on Chip Select 0 and Chip
Read to Write
Wait State
Chip Select
Wait State
NWE_CYCLE
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12